ST802RT1BFR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST802RT1BFR Datasheet PDF : 58 Pages
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Registers and descriptors description
6.2
Table 9.
Register description
Abbreviations
Legend
RW
RO
SC
P
STRAP
LH
LL
ST802RT1A, ST802RT1B
Description
Read/write
Read only
Self-clearing
Constant
Bit with strap value
Latched high
Latched low
Table 10. RN00 [0d00, 0x00]: Control register
Bit Bit name
Description
Default
1 -> software reset, reset in process
15
Soft reset
0 -> normal operation
This bit, which is self-clearing, returns 1 until the reset process
is complete. After this reset the configuration is not re-strapped.
1 -> Loop-back enabled
14
Local loop- 0 -> Normal operation
back
Local loop-back passes data from transmitting to receiving
serial conversion analog logic.
13
Speed
selection
1 -> 100 Mb/s
0 -> 10 Mb/s
Ignored if auto-negotiation is enabled
1 -> Auto-negotiation is enabled
Auto-
0 -> Auto-negotiation is disabled
12 negotiation Bits 8 and 13 of this register are ignored if this bit is set high.
enable
Not available in FX-mode (auto-negotiation always disabled)
11
Power-down
1 -> Power down
0 -> Normal operation
1 -> Isolates the core from the MII, with the exception of the
serial management
0 -> Normal operation.
10
Isolate When this bit is set to ‘1’, related pad outputs are forced to tri-
state, inputs are ignored.
MII isolate mode can be activated at initialization by strapping
00000 on physical address.
Auto- 1 -> Restarts Auto-negotiation process (ignored if Auto-
9 negotiation negotiation is disabled)
restart 0 -> Normal operation
1 -> full-duplex operation
8 Duplex mode 0 -> Half-duplex operation
Ignored if auto-negotiation is enabled
0
Strap
Strap
Strap
0
Strap
0
Strap
RW
type
RW
RW
RW
RW
RW
RW
RW
RW
Type
SC
-
-
-
-
-
SC
-
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Doc ID 17049 Rev 1
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