STK16C88-3 View Datasheet(PDF) - Simtek Corporation
Part Name
Description
Manufacturer
STK16C88-3 Datasheet PDF : 13 Pages
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1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0FC0 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
The software sequence must be clocked with E
controlled READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ
cycles and not WRITE cycles be used in the
sequence, although it is not necessary that G be
low for the sequence to be valid. After the tSTORE
cycle time has been fulfilled, the SRAM will again be
activated for READ and WRITE operation.
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a
sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of READ
operations must be performed:
1. Read address 0E38 (hex)
Valid READ
2. Read address 31C7 (hex)
Valid READ
3. Read address 03E0 (hex)
Valid READ
4. Read address 3C1F (hex)
Valid READ
5. Read address 303F (hex)
Valid READ
6. Read address 0C63 (hex)
Initiate RECALL cycle
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvola-
tile information is transferred into the SRAM cells.
After the tRECALL cycle time the SRAM will once again
be ready for READ and WRITE operations. The
50
STK16C88-3
RECALL operation in no way alters the data in the
nonvolatile storage elements. The nonvolatile data
can be recalled an unlimited number of times.
HARDWARE PROTECT
The STK16C88-3 offers hardware protection
against inadvertent STORE operation and SRAM
WRITEs during low-voltage conditions. When VCC <
VSWITCH, all software STORE operations and SRAM
WRITEs are inhibited.
LOW AVERAGE ACTIVE POWER
The STK16C88-3 draws significantly less current
when it is cycled at rates slower than 35ns. Figure 2
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
perature range, VCC = 3.6V, 100% duty cycle on chip
enable). Figure 3 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK16C88-3 depends on the following
items: 1) CMOS vs. TTL input levels; 2) the duty
cycle of chip enable; 3) the overall cycle rate for
accesses; 4) the ratio of READs to WRITEs; 5) the
operating temperature; 6) the VCC level; and 7) I/O
loading.
50
40
30
20
TTL
10
CMOS
0
50
100 150 200
Cycle Time (ns)
Figure 2: ICC (max) Reads
Document Control #ML0019 Rev 2.0
9
Jan, 2008
40
30
TTL
20
CMOS
10
0
50
100 150 200
Cycle Time (ns)
Figure 3: ICC (max) Writes
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