SY69753LHI View Datasheet(PDF) - Micrel
Part Name
Description
Manufacturer
SY69753LHI Datasheet PDF : 13 Pages
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Micrel, Inc.
SY69753L
Pin Description
Inputs
Pin Number Pin Name
Type Pin Name
2
RDINP Differential Serial Data Input: These built-in line receiver inputs are connected to the differential
3
RDINN
PECL receive serial data stream. An internal receive PLL recovers the embedded clock
(RCLK) and data (RDOUT) information.
5
REFCLK TTL Input Reference Clock: This input is used as the reference for the internal frequency
synthesizer and the "training" frequency for the receiver PLL to keep it centered in the
absence of data coming in on the RDIN inputs.
26
CD
PECL Carrier Detect: This input controls the recovery function of the Receive PLL and can be
Input
driven by the carrier detect output of optical modules or from external transition
detection circuitry. When this input is HIGH, the input data stream (RDIN) is recovered
normally by the Receive PLL. When this input is LOW the data on the inputs RDIN will
be internally forced to a constant LOW, the data outputs RDOUT will remain LOW, the
Link Fault Indicator output LFIN forced LOW and the clock recovery PLL forced to look
onto the clock frequency generated from REFCLK.
32
DIVSEL1 TTL Input Divider Select: These inputs select the ratio between the output clock frequency
25
DIVSEL2
(RCLK/TCLK) and the REFCLK input frequency as shown in the “Reference Frequency
Selection” table.
16
CLKSEL TTL Input Clock Select: This input is used to select either the recovered clock of the receiver PLL
(CLKSEL = HIGH) or the clock of the frequency synthesizer (CLKSEL = LOW) to the
TCLK outputs.
Outputs
Pin Number Pin Name
Type Pin Name
31
LFIN
TTL
Link Fault Indicator: This output indicates the status of the input data stream RDIN.
Output Active HIGH signal is indicating when the internal clock recovery PLL has locked onto
the incoming data stream. LFIN will go HIGH if CD is HIGH and RDIN is within the
frequency range of the Receive PLL (1000ppm) and will be alternating if not. LFIN is an
asynchronous output.
23
RDOUTN Differential Receive Data Output: These ECL 100K outputs represent the recovered data from the
24
RDOUTP
PECL input data stream (RDIN). This recovered data is specified against the rising edge of
RCLK.
20
RCLKN Differential Clock Output: These ECL 100K outputs represent the recovered clock used to sample
21
RCLKP
PECL the recovered data (RDOUT).
18
TCLKP Differential Clock Output: These ECL 100K outputs represent either the recovered clock (CLKSEL
17
TCLKN
PECL = HIGH) used to sample the recovered data (RDOUT) or the transmit clock of the
frequency synthesizer (CLKSEL = LOW).
9
PLLSP
10
PLLSN
Clock Synthesis PLL Loop Filter: External loop filter pins for the clock synthesis PLL.
14
PLLRN
15
PLLRP
Clock Recovery PLL Loop Filter: External loop filter pins for the receiver PLL.
Power and Ground
Pin Number
27, 28
29, 30
19, 22
Pin Name
VCC
VCCA
VCCO
Type
Pin Name
Power Supply.(1)
Analog Power Supply Voltage.(1)
Output Supply Voltage.(1)
12, 13
1, 4, 6, 7, 8
GND
NC
Ground.
No connect.
11
GNDA
Analog Ground.
Note:
1. VCC, VCCA, VCCO must be the same value.
December 2007
3
M9999-120307-F
hbwhelp@micrel.com or (408) 955-1690
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