Philips Semiconductors
Stereo Continuous Calibration DAC
(CC-DAC)
Preliminary specification
TDA1310A
CHARACTERISTICS
VDD = 5 V; Tamb = 25 °C; measured in Fig.1; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
Supply
VDD
supply voltage
3.0
IDD
supply current
at code 0000H
−
SVRR
supply voltage ripple rejection note 1
−
Digital inputs; pins WS, BCK and DATA
|IIL|
input leakage current LOW VI = 0 V
|IIH|
input leakage current HIGH VI = 5 V
fclk
clock frequency
BR
bit rate data input
fWS
word select input frequency
Timing (see Fig.4)
tr
tf
tCY
tBCKH
tBCKL
tSU;DAT
tHD:DAT
tHD:WS
tSU;WS
rise time
fall time
bit clock cycle time
bit clock pulse width HIGH
bit clock pulse width LOW
data set-up time
data hold time to bit clock
word select hold time
word select set-up time
Analog input; pin Iref
Rref
reference resistor
see Fig.1
Analog outputs; pins IOL and IOR
RES
resolution
VDCC
IFS
TCFS
DC output voltage compliance
full-scale current
full-scale temperature
coefficient
Ibias
bias current
GFS
reference input current to full
scale output current gain
Gbias
reference input current to bias
current gain
−
−
−
−
−
−
−
54
15
15
12
2
2
12
7.4
−
2.0
0.9
−
643
11.9
8.48
TYP.
MAX.
5.0
5.5
3.0
4.0
30
−
−
10
−
10
−
18.4
−
18.4
−
384
−
12
−
12
−
−
−
−
−
−
−
−
−
−
−
−
−
−
11.0
14.6
−
−
1.0
±400 × 10−6
16
VDD − 1
1.1
−
714
785
13.2
14.5
9.42
10.36
UNIT
V
mA
dB
µA
µA
MHz
Mbits/s
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
kΩ
bits
V
mA
µA
May 1994
7