DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

SI9978DW(1999) View Datasheet(PDF) - Vishay Semiconductors

Part Name
Description
Manufacturer
SI9978DW
(Rev.:1999)
Vishay
Vishay Semiconductors 
SI9978DW Datasheet PDF : 6 Pages
1 2 3 4 5 6
Si9978DW
Vishay Siliconix
PIN CONFIGURATION
PIN DESCRIPTION
Pin 1: VDD
VDD is an internally generated voltage. It is connected to this
pin to allow connection of a decoupling capacitor. A minimum
of 1 µF is recommended.
Pin 2: EN/ENA
The EN input allows normal operation when at logic “1”, and
turns all gate drive outputs off when at logic “0”. When the
mode pin is at logic “1”, EN controls the entire H-bridge. When
the mode pin is at logic “0”, this pin becomes the ENABLE pin
for half-bridge A.
Pin 3: DIR/INA
The function of this pin is determined by the MODE pin.
When the MODE pin is at logic “1”, it is the DIR pin, and when
MODE is at logic “0”, it is the INA pin.
As the DIR input, it is the direction control for the H-bridge,
and determines which diagonal pair of power MOSFETs is
active. A logic “1” turns on GTA and enables GBB, while a logic
“0” turns on GTB and enables GBA. When implementing an
anti-phase PWM control, the DIR input serves as the PWM
input.
As the INA pin, it is the input that controls the “A” half-bridge.
When at logic “1”, the high-side MOSFET is turned on, and
when at logic “0”, the low-side MOSFET is turned on.
Pin 4: PWM/ENB
With the mode pin at logic “1”, this pin is the PWM input. It
controls the switching of the active diagonal pair. A logic “1”
turns the active MOSFETs on, while a logic “0” turns it off. The
QS input determines whether the bottom or both bottom and
top MOSFETs are switched. When implementing an
anti-phase PWM control, the PWM input is connected to a
logic “1”. When the mode pin is at logic “0”, this pin becomes
the ENABLE pin for half-bridge B.
Pin 5: QS/INB
With the mode pin at logic “1”, this input determines whether
the bottom MOSFETs of the H-bridge or both bottom and top
MOSFETs switch in response to the PWM signal. A logic “1”
on this input enables only the bottom MOSFETs. This is the
default condition as this pin is pulled up internally. When this
pin is pulled to ground, both the bottom and top MOSFETs are
enabled.
This input controls the B half-bridge when the MODE pin is at
logic “0”. When at logic “1”, the high-side MOSFET is turned
on, and when at logic “0”, the low-side MOSFET is turned on.
Pin 6: MODE
This input determines whether the Si9978 functions as an
H-bridge or as two independent half-bridges. When the
MODE pin is at logic “1”, the Si9978 functions as an H-bridge,
and when MODE is at logic “0”, it functions as two
independent half-bridges.
Pin 7: BRK
When this input and MODE are at logic “1”, both bottom gate
drives are switched high, turning on the bottom MOSFETs.
When this input is at logic “0”, the Si9978 operates normally.
S-60752—Rev. D, 05-Apr-99
4
FaxBack 408-970-5600, request 70011
www.siliconix.com

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]