UJA1076TW/3V3 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

UJA1076TW/3V3

High-speed CAN core system basis chip

NXP Semiconductors. 

NXP Semiconductors

UJA1076

High-speed CAN core system basis chip

6.1 System Controller

6.1.1 Introduction

The system controller manages register configuration and controls the internal functions

of the SBC. Detailed device status information is collected and presented to the

microcontroller. The system controller also provides the reset and interrupt signals.

The system controller is a state machine. The SBC operating modes, and how transitions

between modes are triggered, are illustrated in Figure 3. These modes are discussed in

more detail in the following sections.

6.1.2 Off mode

The SBC switches to Off mode from all other modes if the battery supply drops below the

power-off detection threshold (Vth(det)poff). In Off mode, the voltage regulators are disabled

and the bus systems are in a high-resistive state. The CAN bus pins are floating in this

mode.

As soon as the battery supply rises above the power-on detection threshold (Vth(det)pon),

the SBC goes to Standby mode, and a system reset is executed (reset pulse width of

tw(rst), long or short; see Section 6.5.1 and Table 11).

6.1.3 Standby mode

The SBC will enter Standby mode:

• From Off mode if VBAT rises above the power-on detection threshold (Vth(det)pon)

• From Sleep mode on the occurrence of a CAN or local wake-up event

• From Overtemp mode if the chip temperature drops below the overtemperature

protection release threshold, Tth(rel)otp

• From Normal mode if bit MC is set to 00 or a system reset is performed (see

Section 6.5)

In Standby mode, V1 is switched on. The CAN transceiver will either be in a low-power

state (Lowpower mode; STBCC = 1; see Table 6) with bus wake-up detection enabled or

completely switched off (Off mode; STBCC = 0) - see Section 6.7.1. The watchdog can be

running in Timeout mode or Off mode, depending on the state of the WDOFF pin and the

setting of the watchdog mode control bit (WMC) in the WD_and_Status register (Table 4).

The SBC will exit Standby mode if:

• Normal mode is selected by setting bits MC to 10 (V2 disabled) or 11 (V2 enabled)

• Sleep mode is selected by setting bits MC to 01

• The chip temperature rises above the OTP activation threshold, Tth(act)otp, causing the

SBC to enter Overtemp mode

UJA1076_2

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 02 — 27 May 2010

© NXP B.V. 2010. All rights reserved.

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