UPC1854A View Datasheet(PDF) - NEC => Renesas Technology

Part Name

Description

Manufacturer

UPC1854A

I2C BUS-COMPATIBLE US MTS PROCESSING LSI

NEC => Renesas Technology 

µPC1854A

3. I2C BUS INTERFACE

The µPC1854A uses the I2C bus interface that is developed by Philips. The serial clock line (SCL) and serial

data line (SDA) employ the 2-wire configuration as shown in Figure 3-1.

The µPC1854A contains seven (1 byte 8 bits) write registers and one read register through the I2C bus interface

circuit.

Serial Clock Line (SCL)

The master CPU outputs a serial clock to achieve data synchronization. The µPC1854A receives serial data

based on this clock. The input level is CMOS-compatible. The clock frequency is from 0 to 100 kHz.

Serial Data Line (SDA)

The master CPU outputs data synchronously with the serial clock. The µPC1854A receives this data based on

the serial clock. The input level is CMOS-compatible.

Figure 3-1. Internal Equivalent Circuit of Interface Pins

SCL

SDA

RP

RP

µ PC1854A

No protection diode is provided on the VCC side for the SCL and SDA pins so that the I2C bus line is not pulled

to 0 V when the power is OFF (VCC = 0 V).

18

Data Sheet S12816EJ3V0DS00

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