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UPD160040A View Datasheet(PDF) - NEC => Renesas Technology

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UPD160040A Datasheet PDF : 19 Pages
First Prev 11 12 13 14 15 16 17 18 19
µPD160040A
7. RELATIONSHIP BETWEEN MODE, STB, SRC, ORC, POL AND OUTPUT WAVEFORM
When MODE = H or open and STB is high level, all outputs are reset (shorted) and the gray-scale voltage is output
to LCD in synchronization with the falling edge of STB.
When MODE = L and STB is high level, all outputs became Hi-Z and the gray-scale voltage is output to the LCD in
synchronization with the falling edge of STB.
Also, setting the SRC pin to high level allows the bias current value of the output amplifier to rise temporarily, and
setting the ORC pin to high level allows the output resistance value of the amplifier to lower temporarily.
For the timing and the processing of STB, SRC, or ORC during a high-level period, We recommend a thorough
evaluation of the LCD panel specifications in advance.
(1) MODE = H or open
STB
SRC
High-slew-rate period
ORC
POL
Low-slew-rate period
High output resistance period
Low output resistance period
S2n1
S2n
Voltage selected form V0 to V7
Voltage selected form V8 to V15
Voltage selected form V0 to V7
Voltage selected form V8 to V15 Voltage selected form V0 to V7
Voltage selected form V8 to V15
Reset
Reset
Reset
Data Sheet S15918EJ1V0DS
11

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