W78L516A View Datasheet(PDF) - Winbond

Part Name

Description

Manufacturer

W78L516A

8-BIT MICROCONTROLLER

Winbond 

W78LE516/W78L516A

P4 REGISTER

P4.x

READ

WRITE

P4xCSINV

DATA I/O

RD_CS

MUX 4->1

WR_CS

RD/WR_CS

ADDRESS BUS

EQUAL

REGISTER

P4xAL

P4xAH

Bit Length

Selectable

comparator

REGISTER

P4xCMP0

P4xCMP1

P4xFUN0

P4xFUN1

P4.x INPUT DATA BUS

PIN

P4.x

5.12 In-System Programming (ISP) Mode

The W78L516 equips one 64K byte of main Flash EPROM bank for application program (called AP

FLASH EPROM) and one 4K byte of auxiliary Flash EPROM bank for loader program (called LD

FLASH EPROM). In the normal operation, the microcontroller executes the code in the AP FLASH

EPROM. If the content of AP FLASH EPROM needs to be modified, the W78L516 allows user to

activate the In-System Programming (ISP) mode by setting the CHPCON register. The CHPCON is

read-only by default, software must write two specific values 87H, then 59H sequentially to the

CHPENR register to enable the CHPCON write attribute. Writing CHPENR register with the

values except 87H and 59H will close CHPCON register write attribute. The W78L516 achieves

all in-system programming operations including enter/exit ISP Mode, program, erase, read ... etc,

during device in the idle mode. Setting the bit CHPCON.0 the device will enter in-system programming

mode after a wake-up from idle mode. Because device needs proper time to complete the ISP

operations before awaken from idle mode, software may use timer interrupt to control the duration for

device wake-up from idle mode. To perform ISP operation for revising contents of AP FLASH

EPROM, software located at AP FLASH EPROM setting the CHPCON register then enter idle mode,

after awaken from idle mode the device executes the corresponding interrupt service routine in LD

FLASH EPROM. Because the device will clear the program counter while switching from AP FLASH

EPROM to LD FLASH EPROM, the first execution of RETI instruction in interrupt service routine will

jump to 00H at LD FLASH EPROM area. The device offers a software reset for switching back to AP

FLASH EPROM while the content of AP FLASH EPROM has been updated completely. Setting

CHPCON register bit 0, 1 and 7 to logic-1 will result a software reset to reset the CPU. The

software reset serves as a external reset. This in-system programming feature makes the job easy

and efficient in which the application needs to update firmware frequently. In some applications, the in-

system programming feature make it possible to easily update the system firmware without opening

the chassis.

Note: The ISP Mode operates by supply voltage from 3.3V to 5.5V.

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