WM8150
Production Data
PIN DESCRIPTION
PIN
NAME
TYPE
DESCRIPTION
1
AGND2
Supply
Analogue ground (0V).
2
DVDD1
Supply
Digital core (logic and clock generator) supply (5V)
3
VSMP
Digital input Video sample synchronisation pulse.
4
MCLK
Digital input Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or
any multiple of 2 thereafter depending on input sample mode).
5
DGND
Supply
Digital ground (0V).
6
SEN
Digital input Enables the serial interface when high.
7
DVDD2
Supply
Digital supply (5V/3.3V), all digital I/O pins.
8
SDI
Digital input Serial data input.
9
SCK
Digital input Serial clock.
Digital multiplexed output data bus.
ADC output data (d11:d0) is available in 4-bit multiplexed format as shown below.
A
B
C
D
10
OP[0]
Digital output
d8
d4
d0
OVRNG
11
OP[1]
Digital output
d9
d5
d1
CC0
12
OP[2]
Digital output
d10
d6
d2
CC1
13
OP[3]/SDO Digital output
d11
d7
d3
0
Alternatively, pin OP[3]/SDO may be used to output register read-back data when
address bit 4=1 and SEN has been pulsed high. See Serial Interface description in
Device Description section for further details.
14
AVDD
Supply
Analogue supply (5V)
15
AGND1
Supply
Analogue ground (0V).
16
VRB
Analogue output Lower reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
17
VRT
Analogue output Upper reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
18
VRX
Analogue output Input return bias voltage.
This pin must be connected to AGND via a decoupling capacitor.
19 VRLC/VBIAS Analogue I/O Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be connected to AGND via a decoupling capacitor.
VRLC can be externally driven if programmed Hi-Z.
20
VINP
Analogue input Video input.
w
PD Rev 4.1 February 2005
4