WM8521 View Datasheet(PDF) - Wolfson Microelectronics plc
Part Name
Description
Manufacturer
WM8521 Datasheet PDF : 20 Pages
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WM8521
MASTER CLOCK TIMING
MCLK
tMCLKL
tMCLKH
tMCLKY
Figure 1 Master Clock Timing Requirements
Production Data
Test Conditions
AVDD = 12V, DVDD = 3.3V, AGND / DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
System Clock Timing Information
MCLK Master clock pulse width
tMCLKH
11
high
MCLK Master clock pulse width
tMCLKL
11
low
MCLK Master clock cycle time
tMCLKY
28
MCLK Duty cycle
40:60
60:40
Time from MCLK stopping to
digital reset
1.5
12
UNIT
ns
ns
ns
µs
DIGITAL AUDIO INTERFACE
BCLK
BCH
BCL
BCY
LRCLK
DIN
DS
LRH
LRSU
DH
Figure 2 Digital Audio Data Timing
Test Conditions
AVDD = 12V, DVDD = 3.3V, AGND / DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
Audio Data Input Timing Information
BCLK cycle time
tBCY
50
BCLK pulse width high
tBCH
20
BCLK pulse width low
tBCL
20
LRCLK set-up time to BCLK
tLRSU
10
rising edge
LRCLK hold time from
tLRH
10
BCLK rising edge
DIN set-up time to BCLK
tDS
10
rising edge
DIN hold time from BCLK
tDH
10
rising edge
UNIT
ns
ns
ns
ns
ns
ns
ns
w
PD Rev 4.1 August 2006
8
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