Production Data
DIGITAL AUDIO INTERFACE – SLAVE MODE
BCLK
WM8951 ADCLRC
ADC
ADCDAT
DSP
ENCODER/
DECODER
WM8951
Figure 5 Slave Mode Connection
BCLK
ADCLRC
t
BCH
t
BCL
t
BCY
t
LRH
t
DD
ADCDAT
t
LRSU
Figure 6 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD1, AVDD2, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
ADCLRC set-up time to
BCLK rising edge
tBCY
tBCH
tBCL
tLRSU
ADCLRC hold time from
tLRH
BCLK rising edge
ADCDAT propagation delay
tDD
from BCLK falling edge
TEST CONDITIONS
MIN
TYP
MAX
UNIT
50
ns
20
ns
20
ns
10
ns
10
ns
0
15
ns
w
PD Rev 4.0 May 2005
11