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SAF-XC161CJ-16F20F_02(2002) View Datasheet(PDF) - Infineon Technologies

Part Name
Description
Manufacturer
SAF-XC161CJ-16F20F_02
(Rev.:2002)
Infineon
Infineon Technologies 
SAF-XC161CJ-16F20F_02 Datasheet PDF : 78 Pages
First Prev 71 72 73 74 75 76 77 78
Preliminary
tpD
tpE
CLKOUT
tc14
RD, WR
XC161
Derivatives
Timing Parameters
tpRDY
tpF
tc11
D15-D0
(read)
D15-D0
(write)
READY
Synchronous
READY
Asynchron.
tc19
tc20
Data In
tc21
Data Out
tc19 tc20 tc19 tc20
Not Rdy Ready
tc19 tc20 tc19 tc20
Not Rdy Ready
Figure 20 READY Timing
Note: If the READY input is sampled inactive at the indicated sampling point (“Not Rdy”)
a READY-controlled waitstate is inserted (tpRDY),
sampling the READY input active at the indicated sampling point (“Ready”)
terminates the currently running bus cycle.
Note the different sampling points for synchronous and asynchronous READY.
This example uses one mandatory waitstate (see tpE) before the READY input is
evaluated.
Data Sheet
69
V1.0, 2002-03

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