XRT7250 View Datasheet(PDF) - Exar Corporation

Part Name

Description

Manufacturer

XRT7250

DS3/E3 FRAMER IC

Exar Corporation 

áç

DS3/E3 FRAMER IC

XRT7250

LIST OF FIGURES

REV. 1.1.1

Figure 1.Timing Diagram for Transmit Payload Input Interface, when the XRT7250 Device is operating in both

the DS3 and Loop-Timing Modes ................................................................................................................... 25

Figure 2.Timing Diagram for the Transmit Payload Input Interface, when the XRT7250 Device is operating in

both the DS3 and Local-Timing Modes .......................................................................................................... 25

Figure 3.Timing Diagram for the Transmit Payload Data Input Interface, when the XRT7250 Device is operating

in both the DS3/Nibble and Looped-Timing Modes ........................................................................................ 26

Figure 4.Timing Diagram for the Transmit Payload Data Input Interface, when the XRT7250 Device is operating

in the DS3/Nibble and Local-Timing Modes ................................................................................................... 26

Figure 5.Timing Diagram for the Transmit Overhead Data Input Interface (Method 1 Access) ..................... 27

Figure 6.Timing Diagram for the Transmit Overhead Data Input Interface (Method 2 Access) ..................... 27

Figure 7.Transmit LIU Interface Timing - Framer is configured to update "TxPOS" and "TxNEG" on the rising

edge of "TxLineClk" ........................................................................................................................................ 28

Figure 8.Transmit LIU Interface Timing - Framer is configured to update "TxPOS" and "TxNEG" on the falling

edge of "TxLineClk" ........................................................................................................................................ 28

Figure 9.Receive LIU Interface Timing - Framer is configured to sample "RxPOS" and "RxNEG" on the rising

edge of "RxLineClk" ........................................................................................................................................ 29

Figure 10.Receiver LIU Interface Timing - Framer is configured to sample "RxPOS" and "RxNEG" on the falling

edge of "RxLineClk" ........................................................................................................................................ 29

Figure 11.Receive Payload Data Output Interface Timing ............................................................................. 30

Figure 12.Receive Payload Data Output Interface Timing (Nibble Mode Operation) ..................................... 30

Figure 13.Receive Overhead Data Output Interface Timing (Method 1 - Using RxOHClk) ............................ 31

Figure 14.Receive Overhead Data Output Interface Timing (Method 2 - Using RxOHEnable) ...................... 31

Figure 15.Microprocessor Interface Timing - Intel Type Programmed I/O Read Operations ......................... 32

Figure 16.Microprocessor Interface Timing - Intel Type Programmed I/O Write Operations ......................... 32

Figure 17.Microprocessor Interface Timing - Intel Type Read Burst Access Operation ................................. 33

Figure 18.Microprocessor Interface Timing - Intel Type Write Burst Access Operation ................................. 33

Figure 19.Microprocessor Interface Timing - Motorola Type Programmed I/O Read Operation .................... 34

Figure 20.Microprocessor Interface Timing - Motorola Type Programmed I/O Write Operation .................... 34

Figure 21.Microprocessor Interface Timing - Motorola Type Read Burst Access Operation ......................... 35

Figure 22.Microprocessor Interface Timing - Motorola Type Write Burst Access Operation .......................... 35

Figure 23.Microprocessor Interface Timing - Reset Pulse Width ................................................................... 35

Figure 24.Simple Block Diagram of the Microprocessor Interface Block, within the Framer IC ..................... 36

Figure 25.Behavior of Microprocessor Interface signals during an Intel-type Programmed I/O Read Operation

40

Figure 26.Behavior of the Microprocessor Interface Signals, during an Intel-type Programmed I/O Write Opera-

tion .................................................................................................................................................................. 41

Figure 27.Illustration of the Behavior of Microprocessor Interface signals, during a Motorola-type Programmed

I/O Read Operation ........................................................................................................................................ 42

Figure 28.Illustration of the Behavior of the Microprocessor Interface signal, during a Motorola-type Pro-

grammed I/O Write Operation ........................................................................................................................ 43

Figure 29.Behavior of the Microprocessor Interface Signals, during the Initial Read Operation of a Burst Cycle

(Intel Type Processor) .................................................................................................................................... 44

Figure 30.Behavior of the Microprocessor Interface Signals, during subsequent Read Operations within the

Burst I/O Cycle ............................................................................................................................................... 45

Figure 31.Behavior of the Microprocessor Interface signals, during the Initial Write Operation of a Burst Cycle

(Intel-type Processor) ..................................................................................................................................... 46

Figure 32.Behavior of the Microprocessor Interface Signals, during subsequent Write Operations within the

Burst I/O Cycle ............................................................................................................................................... 47

Figure 33.Behavior of the Microprocessor Interface Signals, during the Initial Read Operation of a Burst Cycle

(Motorola Type Processor) ............................................................................................................................. 48

Figure 34.Behavior the Microprocessor Interface Signals, during subsequent Read Operations within the Burst

I/O Cycle (Motorola-type µC/µP) .................................................................................................................... 49

X

Share Link: