XRT79L73 View Datasheet(PDF) - Exar Corporation
Part Name
Description
Manufacturer
XRT79L73 Datasheet PDF : 71 Pages
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XRT79L73
REV. P1.0.0
PRELIMINARY
ÿþ
3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
• Extraction of ATM cells from PLCP frame or directly
from E3 or DS3 frame
• Termination of PLCP frame
• Supports payload cell de-scrambling
TRANSMIT PACKET PROCESSING
• Inserts PPP packets into data stream
• Maps HDLC data stream directly into DS3 or E3
frame
• Extracts in-band messaging packets
• Supports CRC-16/32, HDLC flag and Idle
sequence generation
RECEIVE PACKET PROCESSING
• Extracts HDLC data stream from DS3 or E3 frame
• Inserts in-band messaging packets
• Detects and removes HDLC flags
UTOPIA/ SYSTEM INTERFACE
• 8/16 bit UTOPIA Level I and II and PPP Multi-PHY
Interface operating at 25, 33 or 50 MHz.
• Compliant with ATM Forum UTOPIA II interface
• Programmable FIFO size for both Transmit and
Receive direction
• Compliant to POS-PHY Level 2 interface
SERIAL INTERFACE
• Serial clock and data interface for accessing DS3/
E3 framer
• Serial clock and data interface for accessing cell/
packet processor
APPLICATIONS
• Digital Access and Cross Connect Systems
• 3G Base Stations
• DSLAMs
• Digital, ATM, WAN and LAN Switches
FIGURE 1. BLOCK DIAGRAM OF THE XRT79L73
RTIP
RRING
Channel 1 of 3
AGC/
Equalizer
TU-3
PCOloHck &
ProceDsastoar
Recov ery
Receiver Block
Jitter
Attenuator
Rx DS3/
E3
Framer
TTIP
TRING
E3CLK
DS3CLK
ClkIN
12.288
MHz
Pulse
Shaper
Timing
Control
Transmitter Block
Clock
Synthesizer
Jitter
Attenuator
Tx DS3/
E3
Framer
Microprocessor Interface
PLCP &
Overhead
HDLC
Controller
PLCP &
Overhead
HDLC
Controller
ATM Cell
Processor
or PPP
Processor
UTOPIA/
POS-PHY
Interface
ATM Cell
Processor
or PPP
Processor
2
UTOPIA/
POS-PHY
Interface
JTAG Test Port
Receive
Utopia
POS-PHY
Interface
Transmit
Utopia
POS-PHY
Interface
PRODUCT ORDERING INFORMATION
PRODUCT NUMBER
XRT79L73IB
PACKAGE TYPE
456 Lead PBGA
OPERATING TEMPERATURE RANGE
-40°C to +85°C
2
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