Si530/531
Table 2. CLK± Output Frequency Characteristics (Continued)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Total Stability
Temp stability = ±7 ppm
—
—
±20 ppm
Temp stability = ±20 ppm
—
— ±31.5 ppm
Temp stability = ±50 ppm
—
— ±61.5 ppm
Powerup Time4
tOSC
—
—
10
ms
Notes:
1. See Section 3. "Ordering Information" on page 7 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Selectable parameter specified by part number.
4. Time from powerup or tristate mode to fO.
Table 3. CLK± Output Levels and Symmetry
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
LVPECL Output Option1
VO
VOD
VSE
LVDS Output Option2
VO
mid-level
swing (diff)
swing (single-ended)
mid-level
VDD – 1.42
1.1
0.55
1.125
—
—
—
1.20
VDD – 1.25 V
1.9
VPP
0.95
VPP
1.275
V
VOD
swing (diff)
0.5
0.7
0.9
VPP
CML Output Option2
2.5/3.3 V option mid-level
VO
1.8 V option mid-level
—
VDD – 1.30
—
—
VDD – 0.36
—
V
V
CMOS Output Option3
2.5/3.3 V option swing (diff)
VOD
1.8 V option swing (diff)
1.10
0.35
1.50
0.425
VOH
IOH = 32 mA
0.8 x VDD
—
1.90
VPP
0.50
VPP
VDD
V
VOL
IOL = 32 mA
—
—
0.4
V
Rise/Fall time (20/80%)
tR, tF
LVPECL/LVDS/CML
—
—
350
ps
CMOS with CL = 15 pF
—
1
—
ns
Symmetry (duty cycle)
SYM LVPECL:
VDD – 1.3 V
(diff)
LVDS:
1.25 V (diff)
45
—
55
%
CMOS:
VDD/2
Notes:
1. 50 to VDD – 2.0 V.
2. Rterm = 100 (differential).
3. CL = 15 pF
Rev. 1.5
3