Description
STM6502, STM6503, STM6504, STM6505
Figure 3.
Block diagram - STM6502, STM6503, STM6504
VCC
VRST COMPARE
SR1
(SRE
STM6504
only)(1)
Logic
tREC
generator
RST
SR0
SRC (STM6502)
TSR (STM6503,
STM6504)
Logic
AM00352a
1. STM6504 only: SR0 and SRE are working independently. SRE is edge-triggered and has a special
debounce time (tDEBOUNCE = 240 ms min.) at the falling edge after a valid reset period.
Figure 4. Block diagram - STM6505
6"!4
6"!44( #/-0!2%
",$
6##
6234 #/-0!2%
6##
32
32
32#
,OGIC
T2%#
GENERATOR
234
!-B
8/29
Doc ID 16101 Rev 5