EP2AGZ350DH35C6ES View Datasheet(PDF) - Unspecified

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EP2AGZ350DH35C6ES

Arria II Device Handbook

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Chapter 10: SEU Mitigation in Arria II Devices

Software Support

10–9

Table 10–8 lists the minimum and maximum estimated clock frequency time for each

CRC calculation for Arria II devices. The minimum CRC calculation time is calculated

using the maximum error detection frequency with a divisor factor 1. The maximum

CRC calculation time is calculated using the minimum error detection frequency with

a divisor factor 8.

Table 10–8. CRC Calculation Time for Arria II Devices

Device

EP2AGX45

EP2AGX65

EP2AGX95

EP2AGX125

EP2AGX190

EP2AGX260

EP2AGZ225

EP2AGZ300

EP2AGZ350

Minimum Time (ms)

73.80

73.80

125.80

125.80

216.00

216.00

225

296

296

Maximum Time (s)

20.40

20.40

34.80

34.80

59.90

59.90

62.44

82.05

82.05

Software Support

The Quartus II software, starting with version 9.1 supports the error detection CRC

feature for Arria II GX devices and starting with version 10.1 supports the error

detection CRC feature for Arria II GZ devices. Enabling this feature in the Device and

Pin Options dialog box generates the CRC_ERROR output to the optional dual-purpose

CRC_ERROR pin.

To enable the error detection feature using the CRC, follow these steps:

1. Open the Quartus II software and load a project using an Arria II device.

2. On the Assignments menu, click Device. The Device dialog box appears.

3. Click Device and Pin Options. The Device and Pin Options dialog box appears.

4. In the Category list, select Error Detection CRC tab.

5. Turn on Enable Error Detection CRC.

6. In the Divide error check frequency by pull-down list, enter a valid divisor as

listed in Table 10–6 on page 10–7.

7. Click OK.

February 2014 Altera Corporation

Arria II Device Handbook Volume 1: Device Interfaces and Integration

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