EP2AGX65EU25C5ES View Datasheet(PDF) - Unspecified

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EP2AGX65EU25C5ES

Arria II Device Handbook

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11–2

Chapter 11: JTAG Boundary-Scan Testing in Arria II Devices

BST Architecture for Arria II Devices

Figure 11–1 shows the Arria II GX HSSI transmitter boundary-scan cell.

Figure 11–1. HSSI Transmitter BSC with IEEE Std. 1149.6 BST Circuitry for Arria II GX Devices

BSCAN

PMA

SDOUT

0

DQ

1

DQ

0

BSTX1

1

AC JTAG

Output

Buffer

OE

0

DQ

1

DQ

0

DQ

1

DQ

0

1

BS0EB

Mission

(DATAOUT)

TX_BUF_OE nOE

Pad

Tx Output

Buffer

Pad

MORHZ

OE Logic

ACJTAG_BUF_OE

0

BSTX0

1

OE

AC JTAG

Output

Buffer

MEM_INIT SDIN SHIFT

CLK

UPDATE HIGHZ AC_TEST

MODE

Capture

Update

Registers

AC_MODE

Arria II Device Handbook Volume 1: Device Interfaces and Integration

December 2013 Altera Corporation

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