MM74C73 View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
Manufacturer
MM74C73 Datasheet PDF : 6 Pages
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October 1987
Revised January 2004
MM74C73
Dual J-K Flip-Flops with Clear and Preset
General Description
The MM74C73 dual J-K flip-flops are monolithic comple-
mentary MOS (CMOS) integrated circuits constructed with
N- and P-channel enhancement transistors. Each flip-flop
has independent J, K, clock and clear inputs and Q and Q
outputs. This flip-flop is edge sensitive to the clock input
and change state on the negative going transition of the
clock pulse. Clear or preset is independent of the clock and
is accomplished by a low level on the respective input.
Features
s Supply voltage range: 3V to 15V
s Tenth power TTL compatible: Drive 2 LPTTL loads
s High noise immunity: 0.45 VCC (typ.)
s Low power: 50 nW (typ.)
s Medium speed operation: 10 MHz (typ.)
Applications
• Automotive
• Data terminals
• Instrumentation
• Medical electronics
• Alarm systems
• Industrial electronics
• Remote metering
• Computers
Ordering Code:
Order Number Package Number
Package Description
MM74C73N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Connection Diagram
Truth Table
tn
tn+1
J
K
Q
0
0
Qn
0
1
0
1
0
1
1
1
Qn
Note: A logic “0” on clear sets Q to logic “0”.
Top View
Preset
Clear
Qn
0
0
0
0
1
1
1
0
0
1
1
Qn
(Note 1)
tn = bit time before clock pulse
tn+1 = bit time after clock pulse
Note 1: No change in output from previous state
Qn
0
0
1
Qn
(Note 1)
© 2004 Fairchild Semiconductor Corporation DS005884
www.fairchildsemi.com
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