MC10H135ML1 View Datasheet(PDF) - ON Semiconductor
Part Name
Description
Manufacturer
MC10H135ML1 Datasheet PDF : 4 Pages
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MC10H135
Dual J-K Master-Slave
Flip-Flop
The MC10H135 is a dual J–K master–slave flip–flop. The device is
provided with an asynchronous set(s) and reset(R). These set and reset
inputs overide the clock.
A common clock is provided with separate J–K inputs. When the
clock is static, the JK inputs do not effect the output. The output states
of the flip flop change on the positive transition of the clock.
• Propagation delay, 1.5 ns Typical
• Power Dissipation, 280 mW Typical/Pkg. (No Load)
• ftog 250 MHz Max
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible
S1 5
J1 7
K1 6
R1 4
C9
S2 12
J2 10
K2 11
R2 13
LOGIC DIAGRAM
Q1
2
Q1
3
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
Q2
15
Q2
14
RS TRUTH TABLE
R
S
Qn + 1
L
L
Qn
L
H
H
H
L
L
H
H
N.D.
N.D. = Not Defined
CLOCK J–K TRUTH TABLE*
J
K
Qn + 1
L
L
Qn
H
L
L
L
H
H
H
H
Qn
*Output states change on
positive transition of clock
for J–K input condition
present.
DIP
PIN ASSIGNMENT
VCC1
1
Q1
2
Q1
3
R1
4
S1
5
K1
6
J1
7
VEE
8
16 VCC2
15 Q2
14 Q2
13 R2
12 S2
11 K2
10 J2
9
C
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
http://onsemi.com
CDIP–16
L SUFFIX
CASE 620
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
MARKING
DIAGRAMS
16
MC10H135L
AWLYYWW
1
16
MC10H135P
AWLYYWW
1
1
10H135
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC10H135L
CDIP–16
25 Units/Rail
MC10H135P
PDIP–16
25 Units/Rail
MC10H135FN PLCC–20
46 Units/Rail
© Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 7
Publication Order Number:
MC10H135/D
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