73K324L View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
73K324L Datasheet PDF : 31 Pages
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73K324L
CCITT V.22bis, V.22, V.21, V.23, Bell 212A
Single-Chip Modem
CONTROL REGISTER 2
D7
CR2
0
100
D6
SPEC
REG
ACCESS
D5
CALL
INIT
D4
TRANSMIT
S1
D3
16 WAY
D2
RESET
DSP
D1
TRAIN
INHIBIT
D0
EQUALIZER
ENABLE
BIT NO.
NAME
CONDITION
DESCRIPTION
D0
Equalizer
0
The adaptive equalizer is in its initialized state.
Enable
1
The adaptive equalizer is enabled. This bit is used in
handshakes to control when the equalizer should
calculate its coefficients.
D1
Train Inhibit
0
The adaptive equalizer is active.
1
The adaptive equalizer coefficients are frozen.
D2
RESET DSP
0
The DSP is inactive and all variables are initialized.
1
The DSP is running based on the mode set by other
control bits
D3
16 Way
0
The receiver and transmitter are using the same decision
plane (based on the Modulator Control Mode).
1
The receiver, independent of the transmitter, is forced
into a 16 point decision plane. Used for QAM
handshaking.
D4
Transmit
0
The transmitter when placed in alternating Mark/Space
S1
mode transmits 0101 . . . . scrambled or not dependent
on the bypass scrambler bit and Modulation mode.
1
When this bit is 1 and only when the transmitter is placed
in alternating Mark/Space mode by CR1 bits D7, D6, an
unscrambled repetitive double dibit pattern of 00 and 11
at 1200 bit/s (S1) is sent.
D5
Call Init
0
The DSP is setup to do demodulation and pattern
detection based on the Various mode bits. Both answer
tones are detected in Demod Mode concurrently; TR D0
is ignored.
1
The DSP decodes call progress, calling tones,
unscrambled mark, and 2100 Hz and 2225 Hz answer
tones.
D6
Special
0
Normal CR3 access.
Register
Access
1
Setting this bit and addressing CR3 allows access to the
SPECIAL REGISTER. See the SPECIAL REGISTER for
details.
D7
N/A
0
Must be 0 for normal operation.
14
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