74ALVC162334ADGG View Datasheet(PDF) - Philips Electronics
Part Name
Description
Manufacturer
74ALVC162334ADGG
Philips Electronics
74ALVC162334ADGG Datasheet PDF : 10 Pages
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Philips Semiconductors
16-bit registered driver with inverted register enable
and 30Ω termination resistors (3-State)
Product specification
74ALVC162334A
FEATURES
• Wide supply voltage range of 1.2 V to 3.6 V
• Complies with JEDEC standard no. 8-1A.
• CMOS low power consumption
• Direct interface with TTL levels
• Current drive ± 24 mA at 3.0 V
• MULTIBYTETM flow-through standard pin-out architecture
• Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
• Output drive capability 50 Ω transmission lines @ 85°C
• Current drive ±24 mA at 3.0 V
• Integrated 30 Ω termination resistors
• Input diodes to accommodate strong drivers
DESCRIPTION
The 74ALVC162334A is an 16-bit universal bus driver. Data flow is
controlled by active low output enable (OE), active low latch enable
(LE) and clock inputs (CP).
When LE is LOW, the A to Y data flow is transparent. When LE is
HIGH and CP is held at LOW or HIGH, the data is latched; on the
LOW to HIGH transient of CP the A-data is stored in the
latch/flip-flop.
The 74ALVC162334A is designed with 30 Ω series resistors in both
HIGH or LOW output stages.
When OE is LOW the outputs are active. When OE is HIGH, the
outputs go to the high impedance OFF-state. Operation of the OE
input does not affect the state of the latch/flip -flop.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
PIN CONFIGURATION
OE 1
Y1 2
Y2 3
GND 4
Y3 5
Y4 6
VCC 7
Y5 8
Y6 9
GND 10
Y7 11
Y8 12
Y9 13
Y10 14
GND 15
Y11 16
Y12 17
VCC 18
Y13 19
Y14 20
GND 21
Y15 22
Y16 23
NC 24
48 CP
47 A1
46 A2
45 GND
44 A3
43 A4
42 VCC
41 A5
40 A6
39 GND
38 A7
37 A8
36 A9
35 A10
34 GND
33 A11
32 A12
31 VCC
30 A13
29 A14
28 GND
27 A15
26 A16
25 LE
SH00198
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
Propagation delay
tPHL/tPLH
An to Yn;
LE to Yn;
VCC = 3.3 V, CL = 50 pF
2.9
3.5
CP to Yn
3.3
fmax
Maximum clock frequency
VCC = 3.3 V, CL = 50 pF
240
CI
Input capacitance
4.0
CI/O
Input/Output capacitance
8.0
CPD
Power dissipation capacitance per buffer
VI = GND to VCC1
transparent mode
Output enabled
10
Output disabled
3
Clocked mode
Output enabled
21
Output disabled
15
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
UNIT
ns
MHz
pF
pF
pF
2000 Mar 14
2
853-2197 23314
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