Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI LSIs
MH16V724AWJ -5, -6
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Timing Diagrams (Note 28)
Read Cycle
tRC
tRAS
tRP
VIH
RAS
VIL
VIH
CAS
VIL
VIH
Address
VIL
VIH
W
VIL
tCRP
tRCD
tCSH
tRSH
tCAS
tRAD
tASR tRAH
ROW
ADDRESS
tASC
tRAL
tCAH
COLUMN
ADDRESS
tRCS
tRPC tCRP
tCPN
tRCH
tASR
tRRH
ROW
ADDRESS
tDZC
tCDD
DQ
VIH
(INPUTS)
VIL
DQ
(OUTPUTS)
VOH
VOL
VIH
OE
VIL
Hi-Z
tCAC
tAA
tCLZ
tRAC
tDZO
Hi-Z
tOFF
DATA VALID
tOEA
tOCH
tOEZ
tODD
Hi-Z
tORH
Note 28
Indicates the don't care input.
VIH(min)≤VIN≤VIH(max) or VIL(min)≤VIN≤VIL(max)
Indicates the invalid output.
MIT-DS-0124-0.0
MITSUBISHI
ELECTRIC
( 10 / 20 )
26/Feb./1997