Philips Semiconductors
Quadruple 2-input NAND Schmitt trigger
Product specification
HEF4093B
gates
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL TYP. MAX.
Propagation delays
In → On
HIGH to LOW
LOW to HIGH
Output transition times
HIGH to LOW
LOW to HIGH
5
10
tPHL
15
5
10
tPLH
15
5
10
tTHL
15
5
10
tTLH
15
90
185 ns
40
80 ns
30
60 ns
85
170 ns
40
80 ns
30
60 ns
60
120 ns
30
60 ns
20
40 ns
60
120 ns
30
60 ns
20
40 ns
TYPICAL EXTRAPOLATION
FORMULA
63 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
58 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
Dynamic power
dissipation per
package (P)
VDD
V
TYPICAL FORMULA FOR P (µW)
5
1300 fi + ∑(foCL) × VDD2
where
10
6400 fi + ∑(foCL) × VDD2
fi = input freq. (MHz)
15
18 700 fi + ∑(foCL) × VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
4