SDRAM (Rev.0.2)
Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V64S30ATP-8, -10, -12
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
Auto-Refresh @BL=4
CLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
/CS
/RAS
/CAS
tRC
tRCD
/WE
CKE
DQM
A0-8
X
Y
A10
X
A9,11
X
BA0,1
0
0
DQ
Auto-Refresh
Before Auto-Refresh,
all banks must be idle state.
D0 D0 D0 D0
ACT#0
WRITE#0
After tRC from Auto-Refresh,
all banks are idle state.
Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
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