MC10EP101 View Datasheet(PDF) - ON Semiconductor
Part Name
Description
Manufacturer
MC10EP101 Datasheet PDF : 9 Pages
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MC10EP101, MC100EP101
D0d D1a D1b D1c D1d D2a D2b D2c
VCC VCC Q0 Q0 VEE D0a D0b D0c
24 23 22 21 20 19 18 17
32 31 30 29 28 27 26 25
D0c
25
16
D2d VCC 1
24 D0d
D0b
26
15
D3a Q1 2
23 D1a
D0a
27
14
D3b Q1 3
22 D1b
VEE
28
Q0
29
MC10EP101
MC100EP101
13
VCC Q2 4
12
D3c Q2 5
MC10EP101
MC100EP101
21 D1c
20 D1d
Q0
30
11
D3d Q3 6
19 D2a
VCC
31
10
VEE Q3 7
18 D2b
VCC
32
9
NC VCC 8
17 D2c
12345678
9 10 11 12 13 14 15 16
NC VEE D3d D3c VCC D3b D3a D2d
VCC Q1 Q1 Q2 Q2 Q3 Q3 VCC
Warning: All VCC and VEE pins must be externally connected to
Power Supply to guarantee proper operation.
Figure 2. 32−Lead QFN Pinout (Top View)
Figure 1. 32−Lead LQFP Pinout (Top View)
Table 1. PIN DESCRIPTION
PIN
FUNCTION
D0a*−D3d*
ECL Data Inputs
Q0−Q3, Q0−Q3 ECL Data Outputs
VCC
VEE
NC
EP for QFN−32,
only
Positive Supply
Negative Supply
No Connect
The Exposed Pad (EP) on the
QFN−32 package bottom is
thermally connected to the die
for improved heat transfer out
of package. The exposed pad
must be attached to a heat−
sinking conduit. The pad is
electrically connected to VEE.
* Pins will default LOW when left open.
Table 2. TRUTH TABLE
Dna
Dnb Dnc Dnd
Qn Qn
L
L
L
L
L
H
H
X
X
X
H
L
X
H
X
X
H
L
X
X
H
X
H
L
X
X
X
H
H
L
H
H
H
H
H
L
D0a
D0b
Q0
D0c
Q0
D0d
D1a
D1b
Q1
D1c
Q1
D1d
D2a
D2b
Q2
D2c
Q2
D2d
D3a
D3b
Q3
D3c
Q3
D3d
VEE
Figure 3. Logic Diagram
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