The Safe Operating Area figures shown in Figures 7 and 8 are
specified ratings for these devices under the test conditions
shown.
50
20
10
5.0
2.0
1.0
0.5
0.2
0.1
0.05
0.02
0.01
0.005
1.0
10 µs
dc MJ10015
MJ10016
TC = 25°C
BONDING WIRE LIMIT
THERMAL LIMIT (SINGLE PULSE)
SECOND BREAKDOWN LIMIT
2.0 5.0 10 20
50 100 200 500 1000
VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)
Figure 7. Forward Bias Safe Operating Area
50
40 TURN–OFF LOAD LINE
BOUNDARY FOR MJ10016
THE LOCUS FOR MJ10015
30 IS 100 V LESS
u 20
IC
IB1
10
10 VBE(off) = 5.0 V
TC = 25°C
0
0
100
200
300
400
500
VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)
Figure 8. Reverse Bias Switching Safe
Operating Area
MJ10015 MJ10016
SAFE OPERATING AREA INFORMATION
FORWARD BIAS
There are two Iimitations on the power handling ability of a
transistor: average junction temperature and second break-
down. Safe operating area curves indicate IC – VCE limits of
the transistor that must be observed for reliable operation,
i.e., the transistor must not be subjected to greater dissipa-
tion than the curves indicate.
The data of Figure 7 is based on TC = 25_C; TJ(pk) is
variable depending on power level. Second breakdown pulse
limits are valid for duty cycles to 10% but must be derated
when TC ≥ 25_C. Second breakdown limitations do not der-
ate the same as thermal limitations. Allowable current at the
voltages shown on Figure 7 may be found at any case tem-
perature by using the appropriate curve on Figure 9.
REVERSE BIAS
For inductive loads, high voltage and high current must be
sustained simultaneously during turn–off, in most cases, with
the base to emitter junction reverse biased. Under these
conditions the collector voltage must be held to a safe level
at or below a specific value of collector current. This can be
accomplished by several means such as active clamping,
RC snubbing, load line shaping, etc. The safe level for these
devices is specified as Reverse Bias Safe Operating Area
and represents the voltage–current condition allowable dur-
ing reverse biased turn–off. This rating is verified under
clamped conditions so that the device is never subjected to
an avalanche mode. Figure 8 gives the complete RBSOA
characteristics.
100
80
60
40
20
0
0
FORWARD BIAS
SECOND BREAKDOWN
DERATING
THERMAL
DERATING
40
80
120
160
200
TC, CASE TEMPERATURE (°C)
Figure 9. Power Derating
Motorola Bipolar Power Transistor Device Data
10
9
8
7
6
5
IC = 20 A
4
3
2
SEE TABLE 1 FOR CONDITIONS,
1 FIGURE 6 FOR WAVESHAPE.
0
0
1
2
3
4
5
6
7
8
VBE(off), REVERSE BASE VOLTAGE (VOLTS)
Figure 10. Typical Reverse Base Current
versus VBE(off) With No External Base
Resistance
5