NWK914D View Datasheet(PDF) - Zarlink Semiconductor Inc
Part Name
Description
Manufacturer
NWK914D Datasheet PDF : 9 Pages
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NWK914D
Pin Name
Pin Type
SYMBOL Interface
RXC
TTLOP
SDT
TTLOP
TDAT4
TDAT3
TDAT2
TDAT1
TDAT0
TXC
TTLIP
TTLIP
TTLIP
TTLIP
TTLIP
TTLOP
RDAT0
RDAT1
RDAT2
RDAT3
RDAT4
TTLOP
TTLOP
TTLOP
TTLOP
TTLOP
Network Interface
RXIP
RXIN
TXON
TXOP
analog input
analog input
analog output
analog output
10BASE-T Interface
10TXIN
10TXIP
analog input
analog input
Control Pins
N10/100
TTLIP
EQSEL
3 level IP
LBEN
TTLIP
TXOE
TTLIP
TESTIP
test
TEST
test
N/C
Component Connections
REFCLK
TXREF
LFRB
LFRA
LFTB
LFTA
TTLIP
analog input
analog
analog
analog
analog
Power
TTLGND
RDLVCC
RXPLLGND
RXPLLVCC
RXVCC2
RXGND
RXVCC1
TXVCC
TXGND
RXVCC
SUBGND
BGAPGND
TXPLLGND
TXPLLVCC
TDLVCC
TXLVCC
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
6
Pin Number
Pin Description
4
25MHz recovered receive clock. This is aligned with and used to clock
out the 5 bit parallel receive data to the PCS layer.
5
Signal detect output. This output is high when an input signal of sufficient
amplitude is detected on the RXI inputs.
40
The 100BASE-TX transmit input bit 4
41
The 100BASE-TX transmit input bit 3
42
The 100BASE-TX transmit input bit 2
43
The 100BASE-TX transmit input bit 1
44
The 100BASE-TX transmit input bit 0
47
25MHz transmit clock. This is aligned with and used to clock in the 5 bit parallel
100BASE-TX transmit data from the PCS layer.
48
The 100BASE-TX receive output bit 0
49
The 100BASE-TX receive output bit 1
50
The 100BASE-TX receive output bit 2
51
The 100BASE-TX receive output bit 3
52
The 100BASE-TX receive output bit 4
15
+ Differential receive signal input from magnetics
16
– Differential receive signal input from magnetics
22
– Differential transmit line driver outputs to magnetics
23
+ Differential transmit line driver outputs to magnetics
19
The filtered 10BASE-T transmit input (–)
20
The filtered 10BASE-T transmit input (+)
36
18
35
33
37
38
2,3,7,8
10/100 mode selection. A low selects the 10BASE-T mode and enables the
data on pins 10TXIP/N to be outut on the TXOP/N pins. A high selects the
100BASE-TX mode, enabling the 100Mb/s drivers.
Mode select input for equalizer. Normally this pin is left unconnected (floating) for
auto-eq. mode. High selects minimum equalization. Low selects full equalization.
Loopback enable input. A high on this pin selects the loopback mode and low selects
normal operation.
Transmit output enable. A high on this pin selects normal operation. A low on this
pin puts both of the TX drivers in tri-state mode.
Test pin. This pin must be left unconnected for proper operation.
Test pin. This pin must be left unconnected for proper operation.
No connection. This pin must be left unconnected for proper operation.
45
25MHz clock input. An external 25MHz oscillator is input to this pin.
25
TXOP/N line driver current setting pin. Connects to TXGND through a resistor.
10
Differential loop filter pin for receive PLL (see fig.6)
11
Differential loop filter pin for receive PLL (see fig.6)
30
Differential loop filter pin for transmit clock PLL (see fig.6)
31
Differential loop filter pin for transmit clock PLL (see fig.6)
1,39
GND for TTL logic I/Os
6
+5V supply to receive logic
9
GND to receive PLL
12
+5V supply to receive PLL
13
+5V supply to adaptive equalizer and QFB circuits
14
GND to to adaptive equalizer and QFB circuits
17
+5V supply to MLT-3 to NRZI converter
21
+5V supply to transmit line driver circuits
24
GND to transmit line driver circuits
26
+5V supply to on-chip bandgap reference
27
Chip substrate GND connection
28
GND to on-chip bandgap reference
29
GND to to transmit clock-multiplier PLL
32
+5V supply to transmit clock-multiplier PLL
34
+5V supply to transmit logic
46
+5V supply to TTL logic I/Os
Table 1: Pin descriptions
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