NXP Semiconductors
HEF4541B
Programmable timer
VDD
VI
G
VO
DUT
RT
CL
001aag182
Fig 5.
Test data is given in Table 12.
Definitions for test circuit:
DUT - Device Under Test.
RL = Load resistance.
CL = load capacitance.
RT = Termination resistance should be equal to output impedance of Zo of the pulse generator.
Test circuit for measuring switching times
Table 12. Test data
Supply
VDD
5 V to 15 V
Input
VI
VSS or VDD
tr, tf
≤ 20 ns
Load
CL
50 pF
HEF4541B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
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