HIP4080A/81AEVALZ View Datasheet(PDF) - Intersil
Part Name
Description
Manufacturer
HIP4080A/81AEVALZ Datasheet PDF : 14 Pages
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Application Note 9404
1 BHB BHO 20
12V
2 HEN BHS 19
CL
3 DIS
BLO 18
4 VSS
5 OUT
BLS 17
VDD 16
12V
-+
6 IN+
VCC 15
7 IN-
ALS 14
8 HDEL ALO 13
9 LDEL AHS 12
CL
10 AHB AHO 11
100K 100K
A
IS
VBUS
(0VDC TO 80VDC)
CL = GATE LOAD CAPACITANCE
FIGURE 10. HIGH VOLTAGE LEVEL-SHIFT CURRENT TEST
CIRCUIT
1000
500
200
100
50
20
10
5
2
1
12
80V
60V
40V
20V
5 10 20 50 100 200
SWITCHING FREQUENCY (kHz)
500 1000
FIGURE 11. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs
FREQUENCY AND BUS VOLTAGE
Figure 11 shows that the high voltage level-shift current
varies directly with switching frequency. This result should
not be surprising, since Equation 6 can be rearranged to
show the current as a function of frequency, which is the
reciprocal of the switching period, 1/T. The test circuit of
Figure 10 measures quiescent leakage current as well as
the switching component. Notice that the current increases
somewhat with applied bus voltage. This is due to the finite
output resistance of the level-shift transistors in the IC.
Layout Issues
In fast switching, high frequency systems, poor layout can
result in problems. It is crucial to consider PCB layout. The
HIP4080A pinout configuration encourages tight layout by
placing the gate drive output terminals strategically along the
right side of the chip (pin 1 is in the upper left-hand corner).
This provides for short gate and source return leads
connecting the IC with the power MOSFETs.
Minimize the series inductance in the gate drive loop by
running the lead going out to the gate of the MOSFETs from
the IC over the top of the return lead from the MOSFET
sources back to the IC by using a double-sided PCB if
possible. The PC board separates the traces and provides a
small amount of capacitance as well as reducing the loop
inductance by reducing the encircled area of the gate drive
loop. The benefit is that the gate drive currents and voltages
are much less prone to ringing which can similarly modulate
the drain current of the MOSFET. The following table
summarizes some of the layout problems which can occur
and the corrective action to take.
Layout Problems and Effects
The Bootstrap circuit path should also be short to minimize
series inductance that may cause the voltage on the boot-
strap capacitor to ring, slowing down refresh or causing an
overvoltage on the bootstrap bias supply.
A compact power circuit layout (short circuit path between
upper/lower power switches) minimizes ringing on the phase
lead(s) keeping BHS and AHS voltages from ringing
excessively below the VSS terminal which can cause
excessive charge extraction from the substrate and possible
malfunction of the IC.
Excessive gate lead lengths can cause gate voltage ringing
and subsequent modulation of the drain current, thereby
amplifying the Miller Effect.
PROBLEM
EFFECT
Bootstrap circuit path
too long
Inductance may cause voltage on boot-
strap capacitor to ring, slowing down
refresh and/or causing an overvoltage
on the bootstrap bias supply.
Lack of tight power Can cause ringing on the phase lead(s)
circuit layout (long causing BHS and AHS to ring
circuit path between excessively below the VSS terminal
upper/lower power causing excessive charge extraction
switches)
from the substrate and possible
malfunction of the IC.
Excessive gate lead
lengths
Can cause gate voltage ringing and
subsequent modulation of the drain
current and impairs the effectiveness of
the sink driver from minimizing the
miller effect when an opposing switch is
being rapidly turned on.
10
AN9404.3
December 11, 2007
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