AD7827 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD7827 Datasheet PDF : 12 Pages
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AD7827
CIRCUIT DESCRIPTION
The AD7827 consists of a track-and-hold amplifier followed by
a half-flash analog-to-digital converter. This device uses a half-
flash conversion technique where one 4-bit flash ADC is used to
achieve an 8-bit result. The 4-bit flash ADC contains a sampling
capacitor followed by 15 comparators that compare the unknown
input to a reference ladder to get a 4-bit result. This first flash,
i.e., coarse conversion, provides the 4 MSBs. For a full 8-bit
reading to be realized, a second flash, i.e., a fine conversion,
must be performed to provide the 4 LSBs. The 8-bit word is
then placed in the serial shift register.
Figures 2 and 3 below show simplified schematics of the ADC.
When the ADC starts a conversion, the track-and-hold goes into
hold mode and holds the analog input for 120 ns. This is the
acquisition phase as shown in Figure 2 when Switch 2 is in
Position A. At the point when the track-and-hold returns to its
track mode, this signal is sampled by the sampling capacitor as
Switch 2 moves into Position B. The first flash occurs at this
instant and is then followed by the second flash. Typically the
first flash is complete after 100 ns, i.e., at 220 ns, while the end
REFERENCE
R16
15
SAMPLING
A
CAPACITOR R15
VIN
T/H
14
SW2
B
HOLD
R14
13
.
R13
.
.
.
1
R1
TIMING AND
CONTROL
LOGIC
Figure 2. ADC Acquisition Phase
DOUT
REFERENCE
R16
15
SAMPLING
A
CAPACITOR R15
VIN
T/H
14
SW2
B
HOLD
R14
13
.
R13
.
.
.
1
R1
TIMING AND
CONTROL
LOGIC
DOUT
of the second flash, and hence the 8-bit conversion result, is
available at 330 ns. As shown in Figure 4 the track-and-hold
returns to track mode after 120 ns, and so starts the next acqui-
sition before the end of the current conversion. Figure 6 shows
the ADC transfer function.
120ns
TRACK HOLD
t1
CONVST
t2
RFS
SCLK
TRACK
t3
t7
t8
t4
12 345 678
HOLD
t10
DOUT
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Figure 4. Track-and-Hold Timing
TYPICAL CONNECTION DIAGRAM
Figure 5 shows a typical connection diagram for the AD7827.
The serial interface is implemented using three wires; the RFS is
a logic output and the serial clock is continuous. The Receive
Frame Sync signal (RFS) idles high, the falling edge of CONVST
initiates a conversion and the first rising edge of the serial clock
after the end of conversion causes the RFS signal to go low.
This falling edge of RFS is used to drive the RFS on a micro-
processor—see Serial Interface section for more details. VREF is
connected to a voltage source such as the AD780, while VDD is
connected to a voltage source of 3 V ± 10% or 5 V ± 10%. Due
to the proximity of the CONVST and VIN pins, it is recom-
mended to use a 10 nF decoupling capacitor on VIN. When VDD
is first connected the AD7827 powers up in a low current mode,
i.e., power-down. A rising edge on the CONVST pin will cause
the AD7827 to fully power up. For applications where power
consumption is of concern, the automatic power-down at the
end of a conversion should be used to improve power perfor-
mance. See the Power-Down Options section of this data sheet.
SUPPLY
+3V ؎10% OR
+5V ؎10%
10F
0.1F
0V TO 2.5V (VDD = 5V)
0V TO 2V (VDD = 3V)
INPUT
2.5V
AD780
THREE-WIRE
SERIAL INTERFACE
VDD VREF
SCLK
VIN AD7827 DOUT
RFS
GND
CONVST
C/P
Figure 5. Typical Connection Diagram
Figure 3. ADC Conversion Phase
–6–
REV. 0
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