AD7827 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD7827

3 V/5 V, 1 MSPS, 8-Bit, Serial Interface Sampling ADC

Analog Devices 

AD7827

POWER-UP TIMES

The AD7827 has a 1 µs power-up time when using an external

reference and a 25 µs power-up time when using the on-chip

reference. When VDD is first connected, the AD7827 is in a low

current mode of operation. In order to carry out a conversion

the AD7827 must first be powered up. The AD7827 is pow-

ered up by a rising edge on the CONVST pin and a conversion

is initiated on the falling edge of CONVST. Figure 9 shows

how to power up the AD7827 when VDD is first connected or

after the ADC has been powered down using the CONVST pin

when using either the on-chip, or an external, reference. When

using an external reference the falling edge of CONVST may

occur before the required power-up time has elapsed; however,

the conversion will not be initiated on the falling edge of

CONVST but rather at the moment when the part has com-

pletely powered up, i.e., after 1 µs. If the falling edge of

CONVST occurs after the required power-up time has elapsed,

it is upon this falling edge that a conversion is initiated. When

using the on-chip reference, it is necessary to wait the required

power-up time of approximately 25 µs before initiating a con-

version, i.e., a falling edge on CONVST may not occur before

the required power-up time has elapsed, when VDD is first con-

nected or after the AD7827 has been powered down using the

CONVST pin as shown in Figure 9.

VDD

CONVST

EXTERNAL REFERENCE

tPOWER-UP

1␮s

For example, if the AD7827 is operated in a continuous sam-

pling mode, with a throughput rate of 100 kSPS and using an

external reference, the power consumption is calculated as

follows. The power dissipation during normal operation is

30 mW, VDD = 3 V.

CONVST

tPOWER-UP tCONVERT

1␮s

330ns

POWER-DOWN

tCYCLE

10␮s @ 100kSPS

Figure 10. Automatic Power-Down

If the power-up time is 1 µs and the conversion time is 330 ns

(@ 25°C), the AD7827 can be said to dissipate 30 mW for 1.33 µs

(worst case) during each conversion cycle. If the throughput

rate is 100 kSPS, the cycle time is 10 µs and the average power

dissipated during each cycle is (1.33/10) × (30 mW) = 3.99 mW.

Figure 11 shows the Power vs. Throughput rate for automatic

full power-down.

100

10

VDD

CONVST

CONVERSION INITIATED HERE

ON-CHIP REFERENCE

tPOWER-UP

25␮s

CONVERSION INITIATED HERE

Figure 9. Power-Up Time

POWER VS. THROUGHPUT

Superior power performance can be achieved by using the

automatic power-down (Mode 2) at the end of a conversion

(see Operating Modes section of this data sheet).

Figure 10 shows how the automatic power-down is implemented

using the CONVST signal to achieve the optimum power per-

formance for the AD7827. The duration of the CONVST pulse

is set to be equal to or less than the power-up time of the de-

vices (see Operating Modes section). As the throughput rate is

reduced, the device remains in its power-down state for longer and

the average power consumption over time drops accordingly.

1

0.1

0

50 100 150 200 250 300 350 400 450 500

THROUGHPUT – kSPS

Figure 11. Power vs. Throughput

0

2048 POINT FFT

–10

SAMPLING

1MSPS

FIN = 30kHz

–20

–30

–40

–50

–60

–70

–80

0

50 100 150 200 250 300 350 400 450 500

FREQUENCY – Hz

Figure 12. AD7827 SNR

–8–

REV. 0

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