Output Logic, Registered(1)
Output Logic, Combinatorial(1)
S2 = 0
S1
S0
0
0
1
0
1
1
Terms in
D/T1
D/T2
8
4
12
4(1)
8
4
Output Configuration
Registered (Q1); Q2 FB
Registered (Q1); Q2 FB
Registered (Q1); D/T2 FB
Output
S3 Configuration
0 Active Low
1 Active High
S6
Q1 CLOCK
0 CK1
1 CK1 • PIN1
S4 Register 1 Type
0D
1T
S7
Q2 CLOCK
0 CK2
1 CK2 • PIN1
S5 Register 2 Type
0D
1T
S5
X
X
X
1
0
Note:
S2 = 1
Terms in
S1
S0 D/T1 D/T2 Output Configuration
0
0
4(1)
4
Combinatorial (8 Terms);
Q2 FB
0
1
4
4
Combinatorial (4 Terms);
Q2 FB
1
0
4(1)
4(1)
Combinatorial (12 Terms);
Q2 FB
1
1
4(1)
4
Combinatorial (8 Terms);
D/T2 FB
1
1
4
4
Combinatorial (4 Terms);
D/T2 FB
1. These four terms are shared with D/T1.
Clock Option
Note: 1. These diagrams show equivalent logic functions, not
necessarily the actual circuit implementation.
8 ATF2500C Family
0777I–PLD–4/03