MAX8952 View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

MAX8952

2.5A Step-Down Regulator with Remote Sense in 2mm x 2mm WLP

Maxim Integrated 

MAX8952

2.5A Step-Down Regulator

with Remote Sense in 2mm x 2mm WLP

SDA

SCL

MASTER

TRANSMITTER/RECEIVER

SLAVE RECEIVER

SLAVE

TRANSMITTER/RECEIVER

Figure 11. I2C Master/Slave Configuration

a STOP condition (see the Acknowledge section for

more information). The STOP condition frees the bus.

To issue a series of commands to the slave, the master

can issue REPEATED START (Sr) commands instead of

a STOP command to maintain control of the bus. In

general, a REPEATED START command is functionally

equivalent to a regular START command.

When a STOP condition or incorrect address is detect-

ed, the IC internally disconnects SCL from the serial

interface until the next START condition, minimizing dig-

ital noise and feedthrough.

System Configuration

A device on the I2C bus that generates a message is

called a transmitter and a device that receives the mes-

sage is a receiver. The device that controls the mes-

sage is the master and the devices that are controlled

by the master are called slaves. See Figure 11.

Acknowledge

The number of data bytes between the START and

STOP conditions for the transmitter and receiver are

unlimited. Each 8-bit byte is followed by an acknowl-

edge bit. The acknowledge bit is a low-level signal put

on SDA by the receiver during which time the master

generates an extra acknowledge-related clock pulse. A

slave receiver that is addressed must generate an

acknowledge after each byte it receives. Also, a master

receiver must generate an acknowledge after each

byte it receives that has been clocked out of the slave

transmitter. See Figure 12.

The device that acknowledges must pull down the SDA

line during the acknowledge clock pulse, so that the

SDA line is stable low during the high period of the

SDA OUTPUT

FROM TRANSMITTER

SDA OUTPUT

FROM RECEIVER

D7 D6

D0

NOT ACKNOWLEDGE

SCL FROM

MASTER

ACKNOWLEDGE

1

2

8

9

START CONDITION

CLOCK PULSE FOR

ACKNOWLEDGEMENT

Figure 12. I2C Acknowledge

acknowledge clock pulse (setup and hold times must

also be met). A master receiver must signal an end of

data to the transmitter by not generating an acknowl-

edge on the last byte that has been clocked out of the

slave. In this case, the transmitter must leave SDA high

to enable the master to generate a STOP condition.

Register Reset

The I2C resisters reset back to their default values when

the voltage at either IN1 or VDD drops below the

corresponding UVLO threshold (see the Electrical

Characteristics table).

Update of Output Operation Mode

If updating the output voltage or Operation Mode regis-

ter for the mode that the IC is currently operating in, the

Maxim Integrated

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