IMSA110 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

IMSA110

IMAGE AND SIGNAL PROCESSING SUB–SYSTEM

STMicroelectronics 

IMSA110

Figure 4 : Detailed Block Diagram of the Backend Post-processing Unit

Clock

cycle

1

2

3

Cascade input pads

22

MUX

22

negative overflow

1

positive overflow

1

DATA TRANSFORMATION

22

UNIT

Prescaler

Over/under select

(Isbs) 2

8

6

USR

LSR

64 x 32 bit RAM

Cascade Adder

22

22

Shifter [8:0]

From MAC array

22

1

Rounding

Rectifier

22

STATISTICS MONITOR

Min/max buffer

22

Min/max register

22

Comparator GT/LT

Over/undershoot count

22

Over/undershoot buffer

Control

32

Y bus

[26:22] 5

DATA NORMALIZER

[21:0]

32

Shifter -2 to 14

Zero data

4

Byte select

from

BCR

8

22

MUX

1

22

Rounding

22

Output Adder

22

5

[21:14] 8

8

[7:0]

6

MUX

[13:8]

MUX

8

8

[21:14]

[7:0]

6

22

Cascade output pads

7/26

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