2.5.10.2 MII Mode Timing
Table 25. MII Mode Signal Timing
No.
Characteristics
803 ETHRX_DV, ETHRXD[0–3], ETHRX_ER to ETHRX_CLK rising edge set-up time
804 ETHRX_CLK rising edge to ETHRX_DV, ETHRXD[0–3], ETHRX_ER hold time
805 ETHTX_CLK to ETHTX_EN, ETHTXD[0–3], ETHTX_ER output delay
• 1.1 V core
• 1.2 V core
Min Max Unit
3.5
—
ns
3.5
—
ns
1
14.6
ns
1
12.6
ns
ETHRX_CLK
ETHRX_DV
ETHRXD[0–3]
ETHRX_ER
803
804
Valid
ETHTX_CLK
805
ETHTX_EN
ETHTXD[0–3]
ETHTX_ER
Valid
Valid
Figure 24. MII Mode Signal Timing
2.5.10.3 RMII Mode
Table 26. RMII Mode Signal Timing
1.1 V Core
No.
Characteristics
Min Max
806 ETHTX_EN,ETHRXD[0–1], ETHCRS_DV, ETHRX_ER to ETHREF_CLK rising 1.6
—
edge set-up time
807 ETHREF_CLK rising edge to ETHRXD[0–1], ETHCRS_DV, ETHRX_ER hold
1.6
—
time
811 ETHREF_CLK rising edge to ETHTXD[0–1], ETHTX_EN output delay.
3
12.5
1.2 V Core
Min Max
2
—
1.6
—
3
11
Unit
ns
ns
ns
ETHREF_CLK
ETHCRS_DV
ETHRXD[0–1]
ETHRX_ER
ETHTX_EN
ETHTXD[0–1]
806
807
Valid
811
Valid
Valid
Figure 25. RMII Mode Signal Timing
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15
Freescale Semiconductor
35