MX25L3206E
REVISION HISTORY
Revision No. Description
0.01
1. Revised the Table reference in WRSR, SE, BE and CE
2. Revised DMC description
3. Modified ISB1
4. Modified Figure 8. Output Timing
1.0
1. Modified Figure 19. Block Erase (BE) Sequence
2. Modified "Initial Delivery State" description
3. Revised Vcc Supply Minimum Voltage Address Bits
4. Revised Note 4 of Erase And Programming Performance table
5. Removed "Preliminary"
6. Changed wording from DMC to SFDP
7. Modified standby current from 100uA (max.) to 40uA (max.)
8. Revised SFDP sequence description
1.1
1. Removed SFDP sequence description & content table
1.2
1. Added RDSCUR & WRSCUR diagram form
2. Added CS# rising and falling time description
3. Modified tW from 40(typ.)/100(max.) to 5(typ.)/40(max.)
4. Modified tCLQV(15pF loading) from 8ns(max.) to 6ns(max.)
1.3
1. Modified tCHSH/tSHCH from 7ns(min.) to 5ns(min.)
1.4
1. Added Read SFDP (RDSFDP) Mode
2. Modified description for RoHS compliance
3. Added 24-ball BGA package information
1.5
1. Updated parameters for DC Characteristics.
2. Updated Erase and Programming Performance.
Page
Date
P17~19 APR/02/2010
P23
P29
P31
P36
MAY/19/2010
P26
P25
P44
P5
P6,10,14,23
P5,29
P23
P6,10,14, JUL/01/2010
P23
P37
NOV/04/2010
P10,27
P27,42
P27
P27
JAN/06/2011
P6,11,15, FEB/23/2012
P24~29,34
P6,50,51
P6,7,50,51,
P57
P5,33
DEC/04/2013
P5,34,49
P/N: PM1568
REV. 1.5, DEC. 04, 2013
58