MAX1060AEEIT View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

MAX1060AEEIT

400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel Interface

Maxim Integrated 

400ksps, +5V, 8-/4-Channel, 10-Bit ADCs

with +2.5V Reference and Parallel Interface

REF

REFADJ

(CH7)

(CH6)

(CH5)

(CH4)

CH3

CH2

CH1

CH0

COM

CLK

ANALOG

INPUT

MULTIPLEXER

CLOCK

AV =

2.05

T/H

CHARGE REDISTRIBUTION

10-BIT DAC

10

SUCCESSIVE-

APPROXIMATION

REGISTER

17kΩ

1.22V

REFERENCE

COMP

CS

WR

CONTROL LOGIC

AND

RD

LATCHES

INT

( ) ARE FOR MAX1060 ONLY.

2

8

2

8

MUX

8

8

TRI-STATE, BIDIRECTIONAL

I/O INTERFACE

D0–D7

8-BIT DATA BUS

MAX1060

MAX1064

HBEN

VDD

VLOGIC

GND

Figure 2. Simplified Functional Diagram of 8-/4-Channel MAX1060/MAX1064

Detailed Description

Converter Operation

The MAX1060/MAX1064 ADCs use a successive-

approximation (SAR) conversion technique and an

input track-and-hold (T/H) stage to convert an analog

input signal to a 10-bit digital output. Their parallel (8 + 2)

output format provides an easy interface to standard

microprocessors (µPs). Figure 2 shows the simplified

internal architecture of the MAX1060/MAX1064.

Single-Ended and

Pseudo-Differential Operation

The sampling architecture of the ADC’s analog com-

parator is illustrated in the equivalent input circuits in

Figures 3a and 3b. In single-ended mode, IN+ is inter-

nally switched to channels CH0–CH7 for the MAX1060

(Figure 3a) and to CH0–CH3 for the MAX1064 (Figure

3b), while IN- is switched to COM (Table 3). In differen-

tial mode, IN+ and IN- are selected from analog input

pairs (Table 4).

In differential mode, IN- and IN+ are internally switched to

either of the analog inputs. This configuration is pseudo-

differential in that only the signal at IN+ is sampled. The

return side (IN-) must remain stable within ±0.5 LSB

(±0.1 LSB for best performance) with respect to GND

during a conversion. To accomplish this, connect a

0.1µF capacitor from IN- (the selected input) to GND.

During the acquisition interval, the channel selected as

the positive input (IN+) charges capacitor CHOLD. At

the end of the acquisition interval, the T/H switch

opens, retaining the charge on CHOLD as a sample of

the signal at IN+.

The conversion interval begins with the input multiplex-

er switching CHOLD from the positive input (IN+) to the

negative input (IN-). This unbalances node zero at the

comparator’s positive input. The capacitive digital-to-

analog converter (DAC) adjusts during the remainder of

the conversion cycle to restore node zero to 0V within

the limits of 10-bit resolution. This action is equivalent to

transferring a 12pF [(VIN+) - (VIN-)] charge from CHOLD

to the binary-weighted capacitive DAC, which in turn

forms a digital representation of the analog input signal.

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