NXP Semiconductors
74HC166; 74HCT166
8-bit parallel-in/serial out shift register
VI
MR input
GND
VI
CP input
GND
VOH
Q7 output
VOL
VM
tW
trec
VM
tPHL
VM
aaa-008822
Fig 8.
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Master reset (MR) pulse width, MR to output (Q7) propagation delay and MR to clock (CP) recovery time.
VI
CE input
GND
VI
PE input
GND
VI
Dn input
GND
VI
DS input
GND
see note (1)
VM
tsu
th
VM
tsu
th
stable
VM
tsu
th
VI
CP input
VM
GND
condition: MR = HIGH
tsu
th
tsu
th
stable
VM
tsu
th
tsu
th
tW
aaa-008823
The shaded areas indicate when the input is permitted to change for predictable output performance
Measurement points are given in Table 8.
(1) CE may change only from HIGH-to-LOW while CP is LOW
Fig 9. Set-up and hold times
74HC_HCT166
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 11 September 2013
© NXP B.V. 2013. All rights reserved.
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