ADP3181JRUZ-REEL View Datasheet(PDF) - ON Semiconductor

Part Name

Description

Manufacturer

ADP3181JRUZ-REEL

5-Bit or 6-Bit Programmable 2-,3-,4-Phase Synchronous Buck Controller

ON Semiconductor 

ADP3181

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VID4 1

28 VCC

VID3 2

27 PWM1

VID2 3

26 PWM2

VID1 4

25 PWM3

VID0 5

24 PWM4

CPUID 6

23 SW1

FBRTN 7 ADP3181 22 SW2

FB 8 TOP VIEW 21 SW3

(Not to Scale)

COMP 9

20 SW4

PWRGD 10

19 GND

EN 11

18 CSCOMP

DELAY 12

17 CSSUM

RT 13

16 CSREF

RAMPADJ 14

15 ILIMIT

Table 3. Pin Function Descriptions

Figure 5. Pin Configuration

Pin No.

1 to 5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20 to 23

24 to 27

28

Name

VID4 to VID0

CPUID

FBRTN

FB

COMP

PWRGD

EN

DELAY

RT

RAMPADJ

ILIMIT

CSREF

CSSUM

CSCOMP

GND

SW4 to SW1

PWM4 to PMW1

VCC

Description

Voltage Identification DAC Inputs. These five pins are pulled up to an internal reference, providing a

Logic 1 if left open. When in normal mode, the DAC output programs the FB regulation voltage based

on the condition of the CPUID pin (see Table 4 and Table 5). Leaving VID4 through VID0 open results in the

ADP3181 going into a “no CPU” mode, shutting off its PWM outputs.

CPU DAC Code Selection Input. When this pin is pulled > 4.5 V, the internal DAC reads its inputs based on

the VR 9 VID table (see Table 4). When this pin is < 4 V, the DAC reads its inputs based on the VR 10 VID

table (see Table 5) and treats CPUID as the VID5 input.

Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.

Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor

between this pin and the output voltage sets the no-load offset point.

Error Amplifier Output and Compensation Point.

Power Good Output. Open-drain output that signals when the output voltage is outside of the proper

operating range.

Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs.

Soft-start Delay and Current Limit Latch-off Delay Setting Input. An external resistor and capacitor

connected between this pin and GND sets the soft-start ramp-up time and the overcurrent latch-off

delay time.

Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the

oscillator frequency of the device.

PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal

PWM ramp.

Current Limit Setpoint/Enable Output. An external resistor from this pin to GND sets the current limit

threshold of the converter. This pin is actively pulled low when the ADP3181 EN input is low, or when VCC

is below its UVLO threshold, to signal to the driver IC that the driver high-side and low-side outputs should

go low.

Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current

sense amplifier and the power good and crowbar functions. This pin should be connected to the common

point of the output inductors.

Current Sense Summing Node. External resistors from each switch node to this pin sum the average

inductor currents together to measure the total output current.

Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the slope of

the load line and the positioning loop response time.

Ground. All internal biasing and the logic output signals of the device are referenced to this ground.

Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused

phases should be left open.

Logic-level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the

ADP3413 or ADP3418. Connecting the PWM3 and/or PWM4 outputs to GND causes that phase to turn off,

allowing the ADP3181 to operate as a 2-, 3-, or 4-phase controller.

Supply Voltage for the Device.

Rev. 0 | Page 7 of 24

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