MAX1203BCPP(1998) View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
MAX1203BCPP Datasheet PDF : 24 Pages
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5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
TMS320CL3x to MAX1202/
MAX1203 Interface
Figure 19 shows an application circuit to interface the
MAX1202/MAX1203 to the TMS320 in external clock mode.
Figure 20 shows the timing diagram for this interface circuit.
Use the following steps to initiate a conversion in the
MAX1202/MAX1203 and to read the results:
1) The TMS320 should be configured with CLKX (trans-
mit clock) as an active-high output clock and CLKR
(TMS320 receive clock) as an active-high input clock.
The TMS320’s CLKX and CLKR are tied together with
the MAX1202/MAX1203’s SCLK input.
2) The MAX1202/MAX1203’s CS is driven low by the
TMS320’s XF_ I/O port to enable data to be clocked
into the MAX1202/MAX1203’s DIN.
3) Write an 8-bit word (1XXXXX11) to the MAX1202/
MAX1203 to initiate a conversion and place the
device into external clock mode. Refer to Table 2 to
select the proper XXXXX bit values for your specific
application.
4) The MAX1202/MAX1203’s SSTRB output is moni-
tored via the TMS320’s FSR input. A falling edge on
the SSTRB output indicates that the conversion is in
progress and data is ready to be received from the
MAX1202/MAX1203.
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits repre-
sent the 12-bit conversion result followed by four
trailing bits, which should be ignored.
6) Pull CS high to disable the MAX1202/MAX1203 until
the next conversion is initiated.
+5V
R* = 10Ω
SUPPLIES
-5V
+3V GND
VDD
GND
VSS VL
+3V DGND
MAX1202
MAX1203
DIGITAL
CIRCUITRY
*OPTIONAL
Figure 18. Power-Supply Grounding Connection
XF
CLKX
TMS320LC3x
CLKR
DX
DR
FSR
CS
SCLK
MAX1202
MAX1203
DIN
DOUT
SSTRB
Figure 19. MAX1202/MAX1203-to-TMS320 Serial Interface
CS
SCLK
DIN
SSTRB
DOUT
START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0
MSB B10 B1 LSB
HIGH
IMPEDANCE
HIGH
IMPEDANCE
Figure 20. TMS320 Serial-Interface Timing Diagram
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