LE82Q35SLJA7 View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

LE82Q35SLJA7

Intel® 3 Series Express Chipset Family

Intel 

7.1.12 DMILCTL—DMI Link Control .................................................... 240

7.1.13 DMILSTS—DMI Link Status ..................................................... 241

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Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33,

82G33 GMCH Only) ....................................................................................... 242

8.1 Integrated Graphics Register Details (D2:F0).......................................... 242

8.1.1 VID2—Vendor Identification .................................................... 243

8.1.2 DID—Device Identification ...................................................... 244

8.1.3 PCICMD2—PCI Command ....................................................... 244

8.1.4 PCISTS2—PCI Status ............................................................. 246

8.1.5 RID2—Revision Identification .................................................. 247

8.1.6 CC—Class Code..................................................................... 247

8.1.7 CLS—Cache Line Size............................................................. 248

8.1.8 MLT2—Master Latency Timer................................................... 248

8.1.9 HDR2—Header Type .............................................................. 249

8.1.10 GMADR—Graphics Memory Range Address ................................ 249

8.1.11 IOBAR—I/O Base Address....................................................... 250

8.1.12 SVID2—Subsystem Vendor Identification .................................. 250

8.1.13 SID2—Subsystem Identification .............................................. 251

8.1.14 ROMADR—Video BIOS ROM Base Address ................................. 251

8.1.15 CAPPOINT—Capabilities Pointer ............................................... 252

8.1.16 INTRLINE—Interrupt Line ....................................................... 252

8.1.17 INTRPIN—Interrupt Pin .......................................................... 252

8.1.18 MINGNT—Minimum Grant ....................................................... 253

8.1.19 MAXLAT—Maximum Latency ................................................... 253

8.1.20 CAPID0—Capability Identifier .................................................. 254

8.1.21 MGGC—GMCH Graphics Control Register................................... 255

8.1.22 DEVEN—Device Enable........................................................... 257

8.1.23 SSRW—Software Scratch Read Write........................................ 259

8.1.24 BSM—Base of Stolen Memory.................................................. 259

8.1.25 HSRW—Hardware Scratch Read Write ...................................... 259

8.1.26 MC—Message Control............................................................. 260

8.1.27 MA—Message Address............................................................ 261

8.1.28 MD—Message Data ................................................................ 261

8.1.29 GDRST—Graphics Debug Reset ............................................... 262

8.1.30 PMCAPID—Power Management Capabilities ID ........................... 263

8.1.31 PMCAP—Power Management Capabilities .................................. 263

8.1.32 PMCS—Power Management Control/Status ................................ 264

8.1.33 SWSMI—Software SMI ........................................................... 265

8.2 IGD Configuration Register Details (D2:F1) ............................................ 266

8.2.1 VID2—Vendor Identification .................................................... 268

8.2.2 DID2—Device Identification .................................................... 268

8.2.3 PCICMD2—PCI Command ....................................................... 269

8.2.4 PCISTS2—PCI Status ............................................................. 270

8.2.5 RID2—Revision Identification .................................................. 271

8.2.6 CC—Class Code Register ........................................................ 271

8.2.7 CLS—Cache Line Size............................................................. 272

8.2.8 MLT2—Master Latency Timer................................................... 272

8.2.9 HDR2—Header Type .............................................................. 273

8.2.10 MMADR—Memory Mapped Range Address ................................. 273

8.2.11 SVID2—Subsystem Vendor Identification .................................. 274

8.2.12 SID2—Subsystem Identification .............................................. 274

8.2.13 ROMADR—Video BIOS ROM Base Address ................................. 275

8.2.14 CAPPOINT—Capabilities Pointer ............................................... 275

8.2.15 MINGNT—Minimum Grant ....................................................... 276

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Datasheet

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