NT68625 View Datasheet(PDF) - Novatek Microelectronics

Part Name

Description

Manufacturer

NT68625

Flat Panel Monitor Controller

Novatek Microelectronics 

NT68665/NT68625

 Supports simultaneous display of up to 4 OSD windows

 Maximum 4 times of global zoom for horizontal and vertical axis

 Separate row zoom control

 Support flexible FG or BG optional transparent, translucent, and opaque effects

 256 palette with 64K color selectable

 Top-bottom flip, left-right mirror and 90 degree / 270 degree rotated

 Flexible Fade-in, Fade-out effect

 Splitting OSD frame supported

Display Output

 Supports single pixel or dual pixel output

 Multi-output interface RSDS/LVDS supported

 Spread spectrum clock (SSC) output, output signals drive current and slew rate control for low

EMI

 Dithering function supports 24-bit quality for 18-bit panel

 Optional Frame Sync or Free Run display synchronization modes

 10-bit programmable gamma correction

 2 channel PWM output for LCD back-light control or volume control

 Display resolution up to SXGA

 Supports sRGB input

Built-in Dual Pixel LVDS Transmitter

 Integrate the Dual Port, 4 Data Channel and Clock-Out Low-Voltage differential LVDS transmitter

to supports single or dual pixel 6/8-bit display data transmission

 Suited for VGA, SVGA, XGA and dual pixel SXGA, UXGA display transmission from controller to

display with very low EMI

Built-in Panel Timing Controller

 Integrate the timing control (TCON) to supports single or dual port column drivers

 Integrate RSDS transmitter to supports RSDS differential output for RSDS Column Drivers

 8 Programmable General Purpose Output provide customized for standard or in-house column

drivers and row drivers

 Flexible flicker detection for 2-line dot inversion

Embedded 8031 On-Chip Microcontroller

 8031 8-bit CMOS Micro-Processor (uP) core

 On-Chip Oscillator ➪ 12MHz~15MHz operating frequency

 64K/128K bytes of on-chip flash memory for program memory, 2K bytes of Mask ROM for ISP

control function and 1,280/1792 Bytes On-Chip RAM

 4 channels 7-Bit resolution A/D Converter

 37 Selectable General Purpose I/O Pins

 10 selectable output channels PWM D/A Converter

 5-vector interrupt structure with two programmable priority levels for uP F8031

 Two built-in master/slave I2C bus interfaces support VESA DDC 2Bi/2B+/CI

 Two DDC2Bi with Selectable 128/256 Bytes EDID-Buffer to internal RAM

MCU Interface

 High speed serial 2-wire IIC bus

Power

 3.3V power supply

2006-02-09

6

Ver. 0.40

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