Functional description
6
Functional description
ST8024L
Throughout this document it is assumed that the reader is familiar with ISO7816
terminology.
6.1
6.2
6.2.1
Power supply
The supply pins for the ST8024L are VDD and GND. VDD should be in the range of 2.7 to
6.5 V. All signals interfacing with the system controller are referred to VDD, therefore VDD
should also supply the system controller. All card reader contacts remain inactive during
power-on or power-off.
The internal circuits are kept in the reset state until VDD reaches Vth2 +VHYS2 and for the
duration of the internal power-on reset pulse, tW (see Figure 4). When VDD falls below Vth2,
an automatic deactivation of the contacts is performed.
A step-up converter is incorporated to generate the 1.8 V (for those devices with the
1.8V pin), 3 V, or 5 V card supply voltage (VCC). The step-up converter should be supplied
separately by VDDP and PGND. Due to the possibility of large transient currents, the two
100 nF capacitors of the step-up converter should be located as near as possible to the
ST8024L and have an ESR less than 350 mΩ.
During power-up, the VDD supply voltage must be applied prior to the VDDP supply voltage
or at the same time
After powering the device, OFF remains low until CMDVCC is set high.
During power-off, OFF falls low when VDD is below the falling threshold voltage.
Voltage supervisor
Without external divider on pin PORADJ
The voltage supervisor surveys the VDD supply. A defined reset pulse of approximately 8 ms
(tW) is used internally to keep the ST8024L inactive during power-on or power-off of the VDD
supply (see Figure 4).
As long as VDD is less than Vth2 + VHYS2, the ST8024L remains inactive regardless of the
levels on the command lines. This state also lasts for the duration of tW after VDD has
reached a level higher than Vth2 + VHYS2. When VDD falls below Vth2, a deactivation
sequence of the contacts is performed.
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Doc ID 17709 Rev 5