Preliminary
TX9956CXBG
INITIALIZATION INTERFACE
PIN NAME
VccOK
Reset*
ColdReset*
BSIZE64*
BufSel
OTHERS
PIN NAME
FMRD
FMSI
FMO
FMCLK
TMODE
I/O
VccOK
I
FUNCTION
Soft (Warm) Reset
I
This signal must be asserted synchronously with MasterClock for a soft reset.
Cold reset
This signal indicates to the processor that the +3.3V(I/O) and +1.2V(Internal)
I
power supply is stable and the processor should initiate a cold reset sequence,
resetting the PLL.
Select the bus width of external SysAD bus interface
BSIZE64* width
I
0
64-bit
1
32-bit
Select the output buffer size
BufSel
buffer size
I
0 16mA Buffer
1 8mA Buffer
I / O FUNCTION
I
Test Signal
Test Signal
I
Test Signal
O
Test Signal
I
Test Mode
I
TX9956CXBG 2004-4-25 11