QL8050-6PQ208I View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

Manufacturer

QL8050-6PQ208I

Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM

QuickLogic Corporation 

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Quad Net

Global Clock Net

GCLK Pin

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There are five Quad-Net local clock networks in each quadrant for a total of 20 in a device.

Each Quad-Net is local to a quadrant. Before driving the columns clock buffers, the quad-net is

driven by the output of a mux which selects between the GCLK input and an internally generated

clock source (see )LJXUH ).

Internally generated clock, or

clock from general routing network

Global Clock

(GCLK) Input

Global Clock Network

FF

tPGCK

tBGCK

Global Clock Buffer

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