S29GL064N90BAI040(2007) View Datasheet(PDF) - Spansion Inc.

Part Name

Description

Manufacturer

S29GL064N90BAI040
(Rev.:2007)

64 Megabit, 32 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 110 nm MirrorBit Process Technology

Spansion Inc. 

Data Sheet

8.4

8.5

8.6

8.7

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,

independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VIO ± 0.3 V.

(Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within

VIO ± 0.3 V, the device is in the standby mode, but the standby current is greater. The device requires

standard access time (tCE) for read access when the device is in either of these standby modes, before it is

ready to read data.

If the device is deselected during erasure or programming, the device draws active current until the operation

is completed.

Refer to the DC Characteristics on page 62 for the standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables

this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the

CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are

changed. While in sleep mode, output data is latched and always available to the system. Refer to the DC

Characteristics on page 62 for the automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When the

RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in

progress, Hi-Z all output pins, and ignores all read/write commands for the duration of the RESET# pulse.

The device also resets the internal state machine to reading array data. The operation that was interrupted

should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device

draws CMOS standby current (ICC5). If RESET# is held at VIL but not within VSS±0.3 V, the standby current is

greater.

The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firmware from the Flash memory.

Refer to the AC Characteristics tables for RESET# parameters and to Figure 15.4 on page 66 for the timing

diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high

impedance state.

November 16, 2007 S29GL-N_01_09

S29GL-N MirrorBit® Flash Family

19

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