MAX5318 View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
MAX5318 Datasheet PDF : 41 Pages
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MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = 5V, VDDIO = 2.7V to 5.5V, VAVSS = -1.25V, VREF = 4.096V, RL = 10kω, TC/SB = M/Z = DGND, CREFO = 100pF, CBYPASS
= 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.)(GAIN = 0x3FFFF and OFFSET = 0x00000.)
(Note 2)
PARAMETER
TIMING CHARACTERISTICS
Serial Clock Frequency
SCLK Period
SYMBOL
CONDITIONS
fSCLK
tCP
Stand-alone, write mode
Stand-alone, read mode and daisy-
chained read and write modes (Note 5)
Stand-alone, write mode
Stand-alone, read mode and daisy-
chained read and write modes
MIN TYP MAX UNITS
50
MHz
12.5
20
ns
80
SCLK Pulse Width High
tCH
40% duty cycle
8
ns
SCLK Pulse Width Low
tCL
40% duty cycle
8
ns
Stand-alone, write mode
8
CS Fall to SCLK Fall Setup Time
tCSSO
First SCLK Stand-alone, read mode
falling edge and daisy-chained read
38
ns
and write modes
CS Fall to SCLK Fall Hold Time
tCSH0
Inactive falling edge preceding first falling
edge
0
ns
SCLK Fall to CS Rise Hold Time
tCSH1 24th falling edge
2
ns
DIN to SCLK Fall Setup Time
tDS
5
ns
DIN to SCLK Fall Hold Time
tDH
4.5
ns
SCLK Rise to DOUT Settle Time
tDOT
CL = 20pF (Note 6)
32
ns
SCLK Rise to DOUT Hold Time
tDOH
CL = 0pF (Note 6)
2
SCLK Fall to DOUT Disable Time
tDOZ
24th active edge deassertion
2
CS Fall to DOUT Enable
tDOE
Asynchronous assertion
2
CS Rise to DOUT Disable
tCSDOZ
Stand-alone, aborted sequence
Daisy-chained, aborted sequence
ns
30
ns
30
ns
35
ns
70
SCLK Fall to READY Fall
SCLK Fall to READY Hold
SCLK Fall to BUSY Fall
CS Rise to READY Rise
CS Rise to SCLK Fall
CS Pulse Width High
SCLK Fall to CS Fall
LDAC Pulse Width
LDAC Fall to SCLK Fall Hold
RST Pulse Width
tCRF
tCRH
tCBF
tCSR
tCSA
tCSPW
tCSF
tLDPW
tLDH
tRSTPW
24th falling-edge assertion, CL = 20pF
24th falling-edge assertion, CL = 0pF
BUSY assertion
CL = 20pF
24th falling edge, aborted sequence
Stand alone
24th falling edge
Last active falling edge
2
5
20
20
100
20
20
20
30
ns
ns
ns
35
ns
ns
ns
ns
ns
ns
ns
Maxim Integrated
8
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