CY7C1061AV33-10BZXI(2011) View Datasheet(PDF) - Cypress Semiconductor
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Description
Manufacturer
CY7C1061AV33-10BZXI Datasheet PDF : 13 Pages
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CY7C1061AV33
Switching Waveforms (continued)
Write Cycle No. 3 (BHE/BLE Controlled)
ADDRESS
CE1
CE2
BHE/BLE
WE
DATA IO
tSA
NOTE 18
tWC
tSCE
tAW
tBW
tPWE
tSD
VALID DATA
tHA
tHD
Truth Table
CE1 CE2 OE WE BLE
HX
XX
X
X
L
XX
X
L
H
LH
L
L
H
LH
L
L H LH H
L HXL
L
L HXL
L
L
H
XL
H
L H HH X
BHE
I/O0–I/O7
X High-Z
X High-Z
L Data Out
H Data Out
L High-Z
L Data In
H Data In
L High-Z
X High-Z
I/O8–I/O15
High-Z
High-Z
Data Out
High-Z
Data Out
Data In
High-Z
Data In
High-Z
Mode
Power Down
Power Down
Read All Bits
Read Lower Bits Only
Read Upper Bits Only
Write All Bits
Write Lower Bits Only
Write Upper Bits Only
Selected, Outputs Disabled
Power
Standby (ISB)
Standby (ISB)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Note
18. During this period, the IOs are in output state and input signals should not be applied.
Document #: 38-05256 Rev. *J
Page 8 of 13
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